Clock-Asynchronous Serial I/O
M30240 Group
Rev.1.00 Sep 24, 2003 Page 215 of 360
Figure 2.65: Operation timing of reception in UART mode
Example of wiring
Example of operation
RXDi
RTSi
TXD
Port
Microcomputer
Transmitter side IC
D0
D1
D7
Start bit
Reception started when transfer
clock is generated by falling edge
of start bit
Sampled “L”
Receive data taken in
BRGi's count
source
Receive enable
bit
RxD
i
Transfer clock
Receive
complete flag
RTS
i
Stop bit
“1”
“0”
“0”
“1”
“H”
“L”
Timing of transfer data 8 bits long applies to the following settings :
•Transfer data length is 8 bits.
•Parity is disabled.
•One stop bit
•RTS function is selected.
Receive interrupt
request bit
“0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transferred from UARTi receive register
to UARTi receive buffer register
(1) Reception enabled
(2) Start reception
(4) Data is
read
(3) Receiving is
completed
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