Clock-Synchronous Serial I/O
M30240 Group
Rev.1.00 Sep 24, 2003 Page 199 of 360
(5) With an external clock selected, perform the following set-up procedure with the CLKi pin input lev-
el = “H” if the CLK polarity select bit = “0,” or with the CLKi pin input level = “L” if the CLK polarity select
bit = “1”:
1. Set receive enable bit to “1”
2. Set transmit enable bit to “1”
3. Write dummy data to the UARTi transmit buffer register
(6) Output from the RTS
pin goes to “L” level as soon as the receive enable bit is set to “1”. This is not
related to the content of the transmit buffer empty flag or the content of the transmit enable bit.
Output from the RTS
pin goes to “H” level when reception starts, and goes to “L” level when reception
is completed. This is not related to the content of the transmit buffer empty flag or the content of the
receive complete flag.
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