Renesas RL78/F13

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RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA

R01UH0368EJ0210 Rev.2.10 1078

Dec 10, 2015

(4) Operation without communication

(a) Start ~ Code ~ Data ~ Data ~ Stop

1: IICS0 = 00000001B

Remark : Generated only when SPIE0 = 1

(5) Arbitration loss operation (operation as slave after arbitration loss)

When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal

INTIICA0 has occurred to check the arbitration result.

(a) When arbitration loss occurs during transmission of slave address data

(i) When WTIM0 = 0

1: IICS0 = 0101×110B

2: IICS0 = 0001×000B

3: IICS0 = 0001×000B

4: IICS0 = 00000001B

Remark : Always generated

: Generated only when SPIE0 = 1

×: Don’t care

ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP

3 4 2

Main Page

Default Chapter7
- Table of Contents7
Chapter 1 Overview33
- Features33
- Applications34
- Product Lineup35
- Function Overview36
- RL78/F14 Functions List36
- RL78/F13 (CAN and LIN Incorporated) Functions List38
- RL78/F13 (LIN Incorporated) Functions List40
- Block Diagram42
- RL78/F14: Block Diagram of R5F10Ppn (N = E, F, G, H, J) 100-Pin Products42
- RL78/F14: Block Diagram of R5F10Pmn (N = G, H, J) 80-Pin Products43
- RL78/F14: Block Diagram of R5F10Pln (N = G, H, J) 64-Pin Products44
- RL78/F14: Block Diagram of R5F10Pgn (N = G, H, J) 48-Pin Products45
- RL78/F14: Block Diagram of R5F10Pmn (N = E, F) 80-Pin Products46
- RL78/F14: Block Diagram of R5F10Pln (N = E, F) 64-Pin Products47
- RL78/F14: Block Diagram of R5F10Pgn (N = D, E, F) 48-Pin Products48
- RL78/F14: Block Diagram of R5F10Pbn (N = D, E) 32-Pin Products49
- RL78/F14: Block Diagram of R5F10Pan (N = D, E) 30-Pin Products50
- 80-Pin Products51
- RL78/F13: Block Diagram of R5F10Bmn (N = E, F, G) (CAN and LIN Incorporated) 80-Pin Products51
- 64-Pin Products52
- RL78/F13: Block Diagram of R5F10Bln (N = C, D, E, F, G) (CAN and LIN Incorporated) 64-Pin Products52
  - RL78/F13: Block Diagram of R5F10Bgn (N = C, D, E, F, G) (CAN and LIN Incorporated) 48-Pin Products53
  - RL78/F13: Block Diagram of R5F10Bbn (N = C, D, E, F, G) (CAN and LIN Incorporated) 32-Pin Products54
- RL78/F13: Block Diagram of R5F10Ban (N = C, D, E, F, G) (CAN and LIN Incorporated) 30-Pin Products55
- 30-Pin Products55
- RL78/F13: Block Diagram of R5F10Amn (N = E, F, G) (LIN Incorporated) 80-Pin Products56
- RL78/F13: Block Diagram of R5F10Aln (N = F, G) (LIN Incorporated) 64-Pin Products57
- RL78/F13: Block Diagram of R5F10Agn (N = F, G) (LIN Incorporated) 48-Pin Products58
- RL78/F13: Block Diagram of R5F10Aln (N = C, D, E) (LIN Incorporated) 64-Pin Products59
- RL78/F13: Block Diagram of R5F10Agn (N = A, C, D, E) (LIN Incorporated) 48-Pin Products60
- RL78/F13: Block Diagram of R5F10Abn (N = A, C, D, E) (LIN Incorporated) 32-Pin Products61
- RL78/F13: Block Diagram of R5F10Aan (N = A, C, D, E) (LIN Incorporated) 30-Pin Products62
- RL78/F13: Block Diagram of R5F10A6N (N = A, C, D, E) (LIN Incorporated) 20-Pin Products63
- Pin Configurations64
- RL78/F14 Pin Configuration for 100-Pin Products64
- RL78/F14 Pin Configuration for 80-Pin Products65
- RL78/F13 Pin Configuration for 80-Pin Products66
- RL78/F14 Pin Configuration for 64-Pin Products67
- RL78/F13 Pin Configuration for 64-Pin Product68
- RL78/F14 Pin Configuration for 48-Pin Products69
- RL78/F13 Pin Configuration for 48-Pin Products70
- RL78/F14 Pin Configuration for 32-Pin Products71
- RL78/F13 Pin Configuration for 32-Pin Products72
- RL78/F14 Pin Configuration for 30-Pin Products73
- RL78/F13 Pin Configuration for 30-Pin Products74
- RL78/F13 Pin Configuration for 20-Pin Products75
- Order Information76
Chapter 2 Pin Functions79
- Pin Function List79
- RL78/F14 100-Pin Products81
- RL78/F13 (CAN and LIN Incorporated) 80-Pin Products83
- RL78/F13 (LIN Incorporated) 80-Pin Products85
- Pins for each Product (Pins Other than Port Pins)87
- Description of Pin Functions100
- P00 to P03 (Port 0)100
- P10 to P17 (Port 1)100
- P30 to P34 (Port 3)102
- P40 to P47 (Port 4)103
- P50 to P57 (Port 5)104
- P60 to P67 (Port 6)105
- P70 to P77 (Port 7)107
- P80 to P87 (Port 8)108
- P90 to P97 (Port 9)109
- P100 to P107 (Port 10)109
- P120 to P127 (Port 12)110
- P130, P137 (Port 13)111
- P140 (Port 14)111
- P150 to P157 (Port 15)112
- VDD, Evdd0, Evdd1, Vss, Evss0, Evss1112
- Reset113
- Regc113
- Recommended Connection of Unused Pins114
Chapter 3 Cpu Architecture120
- Memory Space120
- Internal Program Memory Space146
- Mirror Area150
- Internal Data Memory Space152
- Special Function Register (SFR) Area153
- Extended Special Function Register (2Nd SFR: 2Nd Special Function Register) Area153
- Data Memory Addressing154
- Processor Registers172
- Control Registers172
- General-Purpose Registers175
- ES and CS Registers177
- Special Function Registers (Sfrs)178
- Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)183
- Instruction Address Addressing216
- Relative Addressing216
- Immediate Addressing216
- Table Indirect Addressing217
- Register Direct Addressing218
- Addressing for Processing Data Addresses219
- Implied Addressing219
- Register Addressing219
- Direct Addressing220
- Short Direct Addressing221
- SFR Addressing222
- Register Indirect Addressing223
- Based Addressing224
- Based Indexed Addressing228
- Stack Addressing229
Chapter 4 Port Functions233
- Port Functions233
- Port Configuration235
- Port 0236
- Port 1241
- Port 3252
- Port 4258
- Port 5268
- Port 6278
- Port 7288
- Port 8302
- Port 9312
- Port 10315
- Port 12320
- Port 13327
- Port 14330
- Port 15332
- Registers Controlling Port Function339
- Port Mode Registers (Pmxx)351
- Port Registers (Pxx)352
- Pull-Up Resistor Option Registers (Puxx)354
- Port Input Mode Registers (PIM1, PIM3, PIM5 to PIM7, PIM12)355
- Port Output Mode Registers (POM1, POM6, POM7, POM12)356
- Port Mode Control Registers 7, 9, 12 (PMC7, PMC9, PMC12)357
- A/D Port Configuration Register (ADPC)358
- Port Input Threshold Control Register360
- (PITHL1, PITHL3 to PITHL7, PITHL10, PITHL12, PITHL15)360
- Peripheral I/O Redirection Register 0 (PIOR0)362
- Peripheral I/O Redirection Register 1 (PIOR1)363
- Peripheral I/O Redirection Register 2 (PIOR2)364
- Peripheral I/O Redirection Register 3 (PIOR3)365
- Peripheral I/O Redirection Register 4 (PIOR4)366
- Peripheral I/O Redirection Register 5 (PIOR5)368
- Peripheral I/O Redirection Register 6 (PIOR6)369
- Peripheral I/O Redirection Register 7 (PIOR7)370
- Peripheral I/O Redirection Register 8 (PIOR8)371
- Port Output Slew Rate Register (PSRSEL)372
- SNOOZE Status Output Control Register 0 (PSNZCNT0)373
- SNOOZE Status Output Control Register 1 (PSNZCNT1)374
- SNOOZE Status Output Control Register 2 (PSNZCNT2)375
- SNOOZE Status Output Control Register 3 (PSNZCNT3)376
- Port Mode Select Register (PMS)377
- Port Function Operations378
- Writing to I/O Port378
- Reading from I/O Port378
- Operations on I/O Port378
- Connecting to External Device with Different Potential (3 V)379
- Settings of Port Mode Register and Output Latch When Using Alternate Function381
- Cautions When Using Port Function392
- Cautions on 1-Bit Manipulation Instruction for Port Register N (Pn)392
- Notes on Specifying the Pin Settings393
Chapter 5 Clock Generator394
- Functions of Clock Generator394
- Configuration of Clock Generator397
- Registers Controlling Clock Generator401
- Clock Operation Mode Control Register (CMC)401
- System Clock Control Register (CKC)404
- Clock Operation Status Control Register (CSC)406
- Oscillation Stabilization Time Counter Status Register (OSTC)407
- Oscillation Stabilization Time Select Register (OSTS)409
- Peripheral Enable Registers 0, 1, 2 (PER0, PER1, PER2)411
- Operation Speed Mode Control Register (OSMC)417
- High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV)418
- High-Speed On-Chip Oscillator Trimming Register (HIOTRM)419
- CAN Clock Select Register (CANCKSEL)420
- LIN Clock Select Register (LINCKSEL)421
- Clock Select Register (CKSEL)422
- PLL Control Register (PLLCTL)423
- PLL Status Register (PLLSTS)425
- Fmp Clock Division Register (MDIV)426
- System Clock Oscillator427
- X1 Oscillator427
- XT1 Oscillator427
- High-Speed On-Chip Oscillator431
- PLL Circuit431
- Low-Speed On-Chip Oscillator431
- WDT-Dedicated Low-Speed On-Chip Oscillator431
- Clock Generator Operation432
- Controlling Clock434
- Example of Setting High-Speed On-Chip Oscillator434
- Example of Setting X1 Oscillator436
- Example of Setting XT1 Oscillator437
- Examples of Setting PLL Circuit438
- Example of Setting Low-Speed On-Chip Oscillator440
- CPU Clock Status Transition Diagram441
- Conditions before Changing CPU Clock and Processing after Changing CPU Clock445
- Main System Clock452
- Conditions before Clock Oscillation Is Stopped454
- Usage Notes455
- Cpu/Peripheral Hardware Clock455
- High-Speed On-Chip Oscillator455
Chapter 6 Timer Array Unit456
- Functions of Timer Array Unit458
- Simultaneous Channel Operation Function459
- Bit Timer Operation Function (Channels 1 and 3 Only)460
- LIN-Bus Supporting Function (Channel 7 of Unit 0 Only)461
- Configuration of Timer Array Unit462
- Timer Count Register Mn (Tcrmn)468
- Timer Data Register Mn (Tdrmn)470
- Registers Controlling Timer Array Unit471
- Peripheral Enable Register 0 (PER0)472
- Timer Clock Select Register M (Tpsm)473
- Timer Mode Register Mn (Tmrmn)476
- Timer Status Register Mn (Tsrmn)482
- Timer Channel Enable Status Register M (Tem)483
- Timer Channel Start Register M (Tsm)484
- Timer Channel Stop Register M (Ttm)485
- Timer Input Select Register 0 (TIS0)486
- Timer Input Select Register 1 (TIS1)487
- Timer Input Select Register 2 (TIS2)488
- Timer Output Enable Register M (Toem)489
- Timer Output Register M (Tom)490
- Timer Output Level Register M (Tolm)491
- Timer Output Mode Register M (Tomm)492
- Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2)493
- Port Mode Registers 1, 3, 4, 7, 12 (PM1, PM3, PM4, PM7, PM12)496
- PWM Output Delay Control Register 1 (PWMDLY1)498
- PWM Output Delay Control Register 2 (PWMDLY2)499
- Basic Rules of Timer Array Unit500
- Basic Rules of 8-Bit Timer Operation Function (Channels 1 and 3 Only)502
- Operation Timing of Counter503
- Start Timing of Counter505
- Operation of Counter506
- Channel Output (Tomn Pin) Control511
- Tomn Pin Output Setting512
- Cautions on Channel Output Operation513
- Collective Manipulation of Tomn Bit518
- Timer Interrupt and Tomn Pin Output at Operation Start519
- Independent Channel Operation Function of Timer Array Unit520
  - Operation as External Event Counter526
  - Operation as Frequency Divider531
  - Operation as Input Pulse Interval Measurement535
- Operation as Input Signal High-/Low-Level Width Measurement540
- Operation as Delay Counter545
- Simultaneous Channel Operation Function of Timer Array Unit550
- Operation as PWM Function558
- Operation as Multiple PWM Output Function565
- Cautions When Using Timer Array Unit574
Chapter 7 Timer Rj575
- I/O Pins576
- Timer RJ Counter Register 0 (TRJ0), Timer RJ Reload Register580
- Timer RJ Control Register 0 (TRJCR0)581
- Timer RJ I/O Control Register 0 (TRJIOC0)583
- Timer RJ Mode Register 0 (TRJMR0)585
- Timer RJ Event Pin Select Register 0 (TRJISR0)586
- Port Mode Registers 1, 4 (PM1, PM4)587
- Operation588
- Timer Mode589
- Pulse Output Mode590
- Event Counter Mode591
- Pulse Width Measurement Mode593
- Pulse Period Measurement Mode594
- Coordination with Event Link Controller (ELC)595
- Notes on Timer RJ596
- Procedure for Setting Pins TRJO0 and TRJIO0597
- Functional Restriction in STOP Mode (Event Counter Mode Only)598
Chapter 8 Timer Rd599
- Registers601
- Peripheral Enable Register 1 (PER1)602
- Clock Select Register (CKSEL)603
- Timer RD ELC Register (TRDELC)604
- Timer RD Start Register (TRDSTR)605
- Timer RD Mode Register (TRDMR)606
- Timer RD PWM Function Select Register (TRDPMR)607
- Timer RD Function Control Register (TRDFCR)608
- Timer RD Output Master Enable Register 1 (TRDOER1)610
- Timer RD Output Master Enable Register 2 (TRDOER2)611
- Timer RD Output Control Register (TRDOCR)612
- Timer RD Digital Filter Function Select Register I (Trddfi) (I = 0 or 1)615
- Timer RD Control Register I (Trdcri) (I = 0 or 1)617
- Timer RD I/O Control Register Ai (Trdiorai) (I = 0 or 1)622
- Timer RD I/O Control Register CI (Trdiorci) (I = 0 or 1)624
- Timer RD Status Register I (Trdsri) (I = 0 or 1)626
- Timer RD Interrupt Enable Register I (Trdieri) (I = 0 or 1)630
- Timer RD PWM Function Output Level Control Register I (Trdpocri) (I = 0 or 1)631
- Timer RD Counter I (Trdi) (I = 0 or 1)632
- Timer RD General Registers Ai, Bi, CI, and DI (Trdgrai, Trdgrbi,Trdgrci, Trdgrdi I = 0 or 1)634
- PWM Output Delay Control Register 0 (PWMDLY0)643
- Port Mode Registers (PM1, PM3, PM12)644
- Operation645
- Input Capture Function656
- Output Compare Function660
- PWM Function665
- Reset Synchronous PWM Mode669
- Complementary PWM Mode672
- PWM3 Mode676
- Timer RD Interrupt679
- Notes on Timer RD681
- Count Source682
- Reset Synchronous PWM Mode683
Chapter 9 Real-Time Clock688
- Registers Controlling Real-Time Clock690
- Peripheral Enable Register 0 (PER0)691
- Operation Speed Mode Control Register (OSMC)692
- Timer Input Select Register 1 (TIS1)693
- Timer Input Select Register 2 (TIS2)694
- RTC Clock Select Register (RTCCL)695
- Real-Time Clock Control Register 0 (RTCC0)696
- Real-Time Clock Control Register 1 (RTCC1)697
- Second Count Register (SEC)699
- Hour Count Register (HOUR)700
- Day Count Register (DAY)702
- Week Count Register (WEEK)703
- Month Count Register (MONTH)704
- Watch Error Correction Register (SUBCUD)705
- Bit Watch Error Correction Register (SUBCUDW)706
- Alarm Minute Register (ALARMWM)707
- Real-Time Clock Operation709
- Shifting to HALT/STOP Mode after Starting Operation710
- Reading/Writing Real-Time Clock711
- Setting Alarm of Real-Time Clock713
- Hz Output of Real-Time Clock714
- Example of Watch Error Correction of Real-Time Clock715
Chapter 10 Clock Output/Buzzer Output Controller718
- Configuration of Clock Output/Buzzer Output Controller720
- Clock Select Register (CKSEL)722
- Port Mode Register 14 (PM14)723
- Operations of Clock Output/Buzzer Output Controller724
Chapter 11 Watchdog Timer725
- Configuration of Watchdog Timer726
- Register Controlling Watchdog Timer727
- Operation of Watchdog Timer728
- Setting Overflow Time of Watchdog Timer729
- Setting Window Open Period of Watchdog Timer730
- Setting Watchdog Timer Interval Interrupt731
Chapter 12 A/D Converter732
- Function of A/D Converter733
- Configuration of A/D Converter735
  - Registers Used in A/D Converter737
  - Peripheral Enable Register 0 (PER0)738
- A/D Converter Mode Register 0 (ADM0)739
- A/D Converter Mode Register 1 (ADM1)748
- A/D Converter Mode Register 2 (ADM2)749
- Bit A/D Conversion Result Register (ADCR)752
- Bit A/D Conversion Result Register (ADCRH)753
- Analog Input Channel Specification Register (ADS)754
- Conversion Result Comparison Upper Limit Setting Register (ADUL)757
- A/D Test Register (ADTES)758
- A/D Port Configuration Register (ADPC)759
- A/D Converter Trigger Select Register 0 (ADTRGS0) (RL78/F13 Only)760
- A/D Converter Trigger Select Register 1 (ADTRGS1) (RL78/F13 Only)761
- Port Mode Control Registers 7, 9, and 12 (PMC7, PMC9, PMC12)762
- Port Mode Registers 3, 7 to 10, and 12 (PM3, PM7 to PM10, PM12)763
- A/D Converter Conversion Operations765
- Input Voltage and Conversion Results767
- A/D Converter Operation Modes768
- Software Trigger Mode (Select Mode, One-Shot Conversion Mode)769
- Software Trigger Mode (Scan Mode, Sequential Conversion Mode)770
- Software Trigger Mode (Scan Mode, One-Shot Conversion Mode)771
- Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)772
- Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)773
- Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)774
- Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)775
- Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)776
- Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)777
- Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)778
- Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)779
- A/D Converter Setup Flowchart780
- Setting up Software Trigger Mode781
- Setting up Hardware Trigger No-Wait Mode782
- Setting up Hardware Trigger Wait Mode783
- Setting up Test Mode785
- SNOOZE Mode Function786
- If an Interrupt Is Generated after A/D Conversion Ends787
- If no Interrupt Is Generated after A/D Conversion Ends788
- How to Read A/D Converter Characteristics Table789
- Cautions for A/D Converter791
CHAPTER 13 D/A CONVERTER (RL78/F14 Only)795
- Configuration of D/A Converter796
- D/A Converter Mode Register (DAM)800
- D/A Converter Mode Register 2 (DAM2)801
- D/A Conversion Value Setting Register 0 (DACS0)802
- Port Mode Register 8 (PM8)803
CHAPTER 14 COMPARATOR (RL78/F14 Only)808
- Registers to Control the Comparator810
- Comparator Control Register (CMPCTL)811
- Comparator I/O Select Register (CMPSEL)813
- Comparator Output Monitor Register (CMPMON)814
- A/D Port Configuration Register (ADPC)815
- D/A Converter Mode Register 2 (DAM2)816
- Port Mode Register 4 (PM4)817
- Port Mode Register (PM8)818
- Operation819
- Noise Filter820
- Comparator Interrupts821
- Comparator Setting Flowchart822
Chapter 15 Serial Array Unit824
- Functions of Serial Array Unit825
- Uart (Uart0, Uart1)826
- Configuration of Serial Array Unit828
  - Registers Controlling Serial Array Unit834
  - Peripheral Enable Register 0 (PER0)835
- Serial Clock Select Register M (Spsm)836
- Serial Mode Register Mn (Smrmn)837
- Serial Communication Operation Setting Register Mn (Scrmn)839
- Higher 7 Bits of the Serial Data Register Mn (Sdrmn)842
- Serial Flag Clear Trigger Register Mn (Sirmn)844
- Serial Status Register Mn (Ssrmn)845
- Serial Channel Start Register M (Ssm)847
- Serial Channel Stop Register M (Stm)848
- Serial Channel Enable Status Register M (Sem)849
- Serial Output Enable Register M (Soem)850
- Serial Output Register M (Som)851
- Serial Output Level Register M (Solm)852
- Serial Slave Select Enable Register M (Ssem)853
- Input Switch Control Register (ISC)854
- Noise Filter Enable Register 0 (NFEN0)855
- Port Input Mode Registers 1, 3, 5 to 7, 12 (PIM1, PIM3, PIM5 to PIM7, PIM12)856
- Port Output Mode Registers 1, 6, 7, 12 (POM1, POM6, POM7, POM12)857
- Port Mode Registers 1, 3 to 7, 12 (PM1, PM3 to PM7, PM12)858
- Operation Stop Mode860
- Stopping the Operation by Units861
- Stopping the Operation by Channels862
- Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) Communication864
- Master Transmission866
- Master Reception876
- Master Transmission/Reception886
- Slave Transmission896
- Slave Reception906
- Slave Transmission/Reception913
- Calculating Transfer Clock Frequency923
- Procedure for Processing Errors that Occurred During 3-Wire Serial I/O CSI00, CSI01, CSI10, CSI11) Communication925
- Clock Synchronous Serial Communication with SPI Function926
- Master Transmission930
- Master Reception940
- Master Transmission/Reception950
- Slave Transmission960
- Slave Reception970
- Slave Transmission/Reception977
- Calculating Transfer Clock Frequency987
- Procedure for Processing Errors that Occurred During Clock Synchronous Serial Communication with SPI Function989
- Operation of UART (UART0, UART1) Communication990
- UART Transmission992
- UART Reception1002
- Calculating Baud Rate1009
- Procedure for Processing Errors that Occurred During UART (UART0, UART1) Communication1013
- LIN Communication Operation1014
- LIN Reception1017
- Address Field Transmission1026
- Data Transmission1032
- Data Reception1037
- Stop Condition Generation1042
- Calculating Transfer Rate1044
Chapter 16 Serial Interface Iica1048
- Configuration of Serial Interface IICA1051
- Registers Controlling Serial Interface IICA1054
- IICA Control Register 00 (IICCTL00)1055
- IICA Status Register 0 (IICS0)1060
- IICA Flag Register 0 (IICF0)1062
- IICA Control Register 01 (IICCTL01)1064
- IICA Low-Level Width Setting Register 0 (IICWL0)1066
- Port Mode Register 6 (PM6)1067
- Port Output Mode Register (POM6)1068
- Pin Configuration1069
- Setting Transfer Clock by Using IICWL0 and IICWH0 Registers1070
- Start Conditions1072
- Addresses1073
- Acknowledge (ACK)1074
- Stop Condition1075
- Wait1076
- Canceling Wait1078
- Interrupt Request (INTIICA0) Generation Timing and Wait Control1079
- Address Match Detection Method1080
- Arbitration1081
- Wakeup Function1083
- Communication Reservation1086
- Cautions1090
- Communication Operations1091
- Timing Charts1119
Chapter 17 Lin/Uart Module (Rlin3)1134
- Register Descriptions1139
- LIN Registers for Master Mode1141
- LIN Registers for Slave Mode1169
- Registers for UART1197
- Modes1227
- LIN Reset Mode1229
- LIN Mode1230
- UART Mode1232
- LIN Mode1233
- Data Transmission/Reception1241
- Transmission/Reception Data Buffering1243
- Wake-Up Transmission/Reception1246
- Status1248
- Error Status1250
- UART Mode1256
- Data Transmission/Reception1271
- Buffer Processing of Transmission Data1273
- Status1274
- Error Status1275
- LIN Self-Test Mode1276
- Change to LIN Self-Test Mode1277
- Transmission in LIN Master Self-Test Mode1278
- Reception in LIN Master Self-Test Mode1279
- Transmission in LIN Slave Self-Test Mode1280
- Reception in LIN Slave Self-Test Mode1281
- Terminating LIN Self-Test Mode1282
- Baud Rate Generator1283
- LIN Slave Mode1285
- UART Mode1287
- Noise Filter1288
- Interrupts1290
Chapter 18 Can Interface (Rs-Can Lite)1291
- Input/Output Pins1294
- Register Descriptions1295
- Cani Bit Configuration Register L (Cicfgl) (I = 0)1317
- Cani Bit Configuration Register H (Cicfgh) (I = 0)1318
- Cani Control Register L (Cictrl) (I = 0)1320
- Cani Control Register H (Cictrh) (I = 0)1322
- Cani Status Register L (Cistsl) (I = 0)1324
- Cani Status Register H (Cistsh) (I = 0)1326
- Cani Error Flag Register L (Cierfll) (I = 0)1327
- Cani Error Flag Register H (Cierflh) (I = 0)1330
- CAN Global Configuration Register L (GCFGL)1331
- CAN Global Configuration Register H (GCFGH)1333
- CAN Global Control Register L (GCTRL)1334
- CAN Global Control Register H (GCTRH)1335
- CAN Global Status Register (GSTS)1336
- CAN Global Error Flag Register (GERFLL)1337
- CAN Global Transmit Interrupt Status Register (GTINTSTS)1338
- CAN Timestamp Register (GTSC)1339
- CAN Receive Rule Number Configuration Register (GAFLCFG)1340
- CAN Receive Rule Entry Register Jal (Gaflidlj) (J = 0 to 15)1341
- CAN Receive Rule Entry Register Jah (Gaflidhj) (J = 0 to 15)1342
- CAN Receive Rule Entry Register Jbl (Gaflmlj) (J = 0 to 15)1343
- CAN Receive Rule Entry Register Jbh (Gaflmhj) (J = 0 to 15)1344
- CAN Receive Rule Entry Register Jcl (Gaflplj) (J = 0 to 15)1345
- CAN Receive Rule Entry Register Jch (Gaflphj) (J = 0 to 15)1346
- CAN Receive Buffer Number Configuration Register (RMNB)1347
- CAN Receive Buffer Receive Complete Flag Register (RMND0)1348
- CAN Receive Buffer Register Nal (Rmidln) (N = 0 to 15)1349
- CAN Receive Buffer Register Nah (Rmidhn) (N = 0 to 15)1350
- CAN Receive Buffer Register Nbl (Rmtsn) (N = 0 to 15)1351
- CAN Receive Buffer Register Nbh (Rmptrn) (N = 0 to 15)1352
- CAN Receive Buffer Register Ncl (Rmdf0N) (N = 0 to 15)1353
- CAN Receive Buffer Register Nch (Rmdf1N) (N = 0 to 15)1354
- CAN Receive Buffer Register Ndl (Rmdf2N) (N = 0 to 15)1355
- CAN Receive Buffer Register Ndh (Rmdf3N) (N = 0 to 15)1356
- CAN Receive FIFO Control Register M (Rfccm) (M = 0, 1)1357
- CAN Receive FIFO Status Register M (Rfstsm) (M = 0, 1)1359
- CAN Receive FIFO Pointer Control Register M (Rfpctrm) (M = 0, 1)1361
- CAN Receive FIFO Access Register Mal (Rfidlm) (M = 0, 1)1362
- CAN Receive FIFO Access Register Mah (Rfidhm) (M = 0, 1)1363
- CAN Receive FIFO Access Register Mbl (Rftsm) (M = 0, 1)1364
- CAN Receive FIFO Access Register Mbh (Rfptrm) (M = 0, 1)1365
- CAN Receive FIFO Access Register Mcl (Rfdf0M) (M = 0, 1)1366
- CAN Receive FIFO Access Register Mch (Rfdf1M) (M = 0, 1)1367
- CAN Receive FIFO Access Register Mdl (Rfdf2M) (M = 0, 1)1368
- CAN Receive FIFO Access Register Mdh (Rfdf3M) (M = 0, 1)1369
- Cani Transmit/Receive FIFO Control Register Kl (Cfcclk) (I = 0) (K = 0)1370
- Cani Transmit/Receive FIFO Control Register Kh (Cfcchk) (I = 0) (K = 0)1372
- Cani Transmit/Receive FIFO Status Register K (Cfstsk) (I = 0) (K = 0)1374
- Cani Transmit/Receive FIFO Pointer Control Register K (Cfpctrk) (I = 0) (K = 0)1376
- Cani Transmit/Receive FIFO Access Register Kal (Cfidlk) (I = 0) (K = 0)1377
- Cani Transmit/Receive FIFO Access Register Kah (Cfidhk) (I = 0) (K = 0)1378
- Cani Transmit/Receive FIFO Access Register Kbl (Cftsk) (I = 0) (K = 0)1379
- Cani Transmit/Receive FIFO Access Register Kbh (Cfptrk) (I = 0) (K = 0)1380
- Cani Transmit/Receive FIFO Access Register Kcl (Cfdf0K) (I = 0) (K = 0)1381
- Cani Transmit/Receive FIFO Access Register Kch (Cfdf1K) (I = 0) (K = 0)1382
- Cani Transmit/Receive FIFO Access Register Kdl (Cfdf2K) (I = 0) (K = 0)1383
- Cani Transmit/Receive FIFO Access Register Kdh (Cfdf3K) (I = 0) (K = 0)1384
- Receive FIFO Message Lost Status Register (RFMSTS)1385
- Cani Transmit/Receive FIFO Message Lost Status Register (CFMSTS) (I = 0)1386
- CAN Receive FIFO Interrupt Status Register (RFISTS)1387
- CAN Transmit/Receive FIFO Receive Interrupt Status Register (CFISTS)1388
- Cani Transmit Buffer Control Register P (Tmcp) (I = 0) (P = 0 to 3)1389
- Cani Transmit Buffer Status Register P (Tmstsp) (I = 0) (P = 0 to 3)1391
- Cani Transmit Buffer Transmit Request Status Register (TMTRSTS) (I = 0)1392
- Cani Transmit Buffer Transmit Complete Status Register (TMTCSTS) (I = 0)1393
- Cani Transmit Buffer Transmit Abort Status Register (TMTASTS) (I = 0)1394
- Cani Transmit Buffer Interrupt Enable Register (TMIEC) (I = 0)1395
- Cani Transmit Buffer Register Pal (Tmidlp) (I = 0) (P = 0 to 3)1396
- Cani Transmit Buffer Register Pah (Tmidhp) (I = 0) (P = 0 to 3)1397
- Cani Transmit Buffer Register Pbh (Tmptrp) (I = 0) (P = 0 to 3)1398
- Cani Transmit Buffer Register Pcl (Tmdf0P) (I = 0) (P = 0 to 3)1399
- Cani Transmit Buffer Register Pch (Tmdf1P) (I = 0) (P = 0 to 3)1400
- Cani Transmit Buffer Register Pdl (Tmdf2P) (I = 0) (P = 0 to 3)1401
- Cani Transmit Buffer Register Pdh (Tmdf3P) (I = 0) (P = 0 to 3)1402
- Cani Transmit History Buffer Control Register (Thlcci) (I = 0)1403
- Cani Transmit History Buffer Status Register (Thlstsi) (I = 0)1404
- Cani Transmit History Buffer Access Register (Thlacci) (I = 0)1405
- Cani Transmit History Buffer Pointer Control Register (Thlpctri) (I = 0)1406
- CAN Global RAM Window Control Register (GRWCR)1407
- CAN Global Test Configuration Register (GTSTCFG)1408
- CAN Global Test Control Register (GTSTCTRL)1409
- CAN Global Test Protection Unlock Register (GLOCKK)1410
- CAN RAM Test Register R (Rpgaccr) (R = 0 to 127)1411
- CAN Modes1412
- Channel Modes1414
- Reception Function1419
- Timestamp1421
- Transmission Functions1422
- Transmission Using Transmit Buffers1423
- Transmission Using FIFO Buffers1424
- Transmit History Function1426
- Test Function1427
- Self-Test Mode (Loopback Mode)1428
- Interrupt1429
- RAM Window1433
- Initial Settings1434
- Clock Setting1436
- Communication Speed Setting1437
- Receive Rule Setting1439
- Buffer Setting1440
- Reception Procedure1442
- FIFO Buffer Reading Procedure1444
- Transmission Procedure1447
- Procedure for Transmission from Transmit/Receive FIFO Buffers1450
- Transmit History Buffer Reading Procedure1453
- Test Settings1454
- Protection Unlock Procedure1455
- RAM Test Setting Procedure1456
- Notes on the CAN Module1457
Chapter 19 Dtc1458
- Registers1460
- Allocation of DTC Control Data Area and DTC Vector Table Area1462
- DTC Control Data Allocation1463
- DTC Vector Table1464
- Peripheral Enable Register 1 (PER1)1468
- DTC Activation Enable Register I (Dtceni) (I = 0 to 5)1469
- DTC Base Address Register (DTCBAR)1472
- DTC Control Register J (Dtccrj) (J = 0 to 23)1473
- DTC Block Size Register J (Dtblsj) (J = 0 to 23)1474
- DTC Transfer Count Reload Register J (Dtrldj) (J = 0 to 23)1475
- High-Speed DTC Channel Select Register 0 (SELHS0)1476
- High-Speed DTC Channel Select Register 1 (SELHS1)1477
- High-Speed DTC Control Register M (HDTCCR0/1) (M = 0, 1)1478
- High-Speed DTC Transfer Count Register M (HDTCCT0/1) (M = 0, 1)1479
- DTC Transfer Count Reload Register M (HDTRLD0/1) (M = 0, 1)1480
- Operation1481
- Normal Mode1483
- Repeat Mode1485
- Chain Transfers1489
- High-Speed Transfer Operation1491
- Notes on DTC1492
- DTC Pending Instruction1493
- Number of DTC Execution Clock Cycles1494
- Number of High-Speed DTC Execution Clock Cycles1495
- DTC Response Time1496
- Operation in Standby Mode Status1497
CHAPTER 20 EVENT LINK CONTROLLER (ELC) (RL78/F14 Only)1498
- Registers1499
- Event Output Destination Select Register N (Elselrn) (N = 00 to 25)1500
- Timer Input Select Register 01503
- Operation1504
Chapter 21 Interrupt Functions1505
- Interrupt Sources and Configuration1506
- Registers Controlling Interrupt Functions1516
- Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L)1522
- Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L)1524
  - Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L)1526
  - External Interrupt Rising Edge Enable Registers (EGP0, EGP1 External Interrupt Falling Edge Enable Registers (EGN0, EGN1)1529
- Interrupt Source Determination Flag Register 0 (INTFLG0)1531
- Interrupt Mask Register (INTMSK)1534
- Input Switch Control Register (ISC)1535
- Program Status Word (PSW)1536
- Interrupt Servicing Operations1537
- Software Interrupt Request Acknowledgment1540
- Interrupt Servicing During Division Instruction1544
- Interrupt Request Hold1546
Chapter 22 Key Interrupt Function1547
- Configuration of Key Interrupt1548
- Register Controlling Key Interrupt1549
Chapter 23 Standby Function1550
- Registers Controlling Standby Function1551
- Oscillation Stabilization Time Counter Status Register (OSTC)1552
- Oscillation Stabilization Time Select Register (OSTS)1553
- STOP Status Output Control Register (STPSTC)1554
- Standby Function Operation1555
- STOP Mode1562
- SNOOZE Mode1568
Chapter 24 Reset Function1573
- Register for Confirming Reset Source1584
- POR/CLM Reset Confirmation Register (POCRES)1585
Chapter 25 Power-On-Reset Circuit1587
- Configuration of Power-On-Reset Circuit1588
- Cautions for Power-On-Reset Circuit1591
Chapter 26 Voltage Detector1593
- Configuration of Voltage Detector1594
- Voltage Detection Register (LVIM)1595
- Voltage Detection Level Register (LVIS)1596
- Operation of Voltage Detector1599
- When Used as Interrupt Mode1601
- When Used as Interrupt and Reset Mode1603
- Cautions for Voltage Detector1609
- Delay from the Time LVD Reset Source Is Generated until the Time LVD Reset Has Been Generated or Released1610
Chapter 27 Safety Functions1611
- Registers Used by Safety Functions1613
- Operation of Safety Functions1614
- CRC Operation Function (General-Purpose CRC)1618
- RAM-ECC Function1622
- CPU Stack Pointer Monitor Function1628
- Clock Monitor1631
- RAM Guard Function1632
- SFR Guard Function1633
- Invalid Memory Access Detection Function1634
- Frequency Detection Function1637
- A/D Test Function1640
- Digital Output Signal Level Detection Function for I/O Ports1645
Chapter 28 Regulator1646
Chapter 29 Option Byte1647
- On-Chip Debug Option Byte (000C3H/ 020C3H)1648
- Format of User Option Byte1649
- Format of On-Chip Debug Option Byte1653
- Setting of Option Byte1654
Chapter 30 Flash Memory1655
- Serial Programming Using Flash Memory Programmer1657
- Programming Environment1659
- Serial Programming Using External Device (that Incorporates UART)1661
- Communication Mode1662
- Connection of Pins on Board1663
- Port Pins1664
- Serial Programming Method1665
- Flash Memory Programming Mode1666
- Selecting Communication Mode1667
- Communication Commands1668
- Processing Time for each Command When PG-FP5 Is in Use (Reference Value)1669
- Self-Programming1670
- Self-Programming Procedure1671
- Boot Swap Function1672
- Flash Shield Window Function1674
- Security Settings1675
- Data Flash1677
- Register Controlling Data Flash Memory1678
- Procedure for Accessing Data Flash Memory1679
Chapter 31 On-Chip Debug Function1680
- Connecting E1 On-Chip Debugging Emulator to RL78/F13 or RL78/F141682
- On-Chip Debug Security ID1683
Chapter 32 Bcd Correction Circuit1686
- BCD Correction Circuit Operation1687
Chapter 33 Instruction Set1689
- Conventions Used in Operation List1690
- Description of Operation Column1691
- Description of Flag Operation Column1692
- Operation List1693
Chapter 34 Electrical Specifications (Grade L)1711
- Absolute Maximum Ratings1712
- Oscillator Characteristics1714
- On-Chip Oscillator Characteristics1715
- Subsystem Clock Oscillator Characteristics1716
- PLL Circuit Characteristics1717
- DC Characteristics1718
- Supply Current Characteristics1724
- AC Characteristics1729
- Peripheral Functions Characteristics1732
- Serial Interface IICA1751
- On-Chip Debug (UART)1752
Chapter 35 Electrical Specifications (Grade K)1762
- Absolute Maximum Ratings1763
- Oscillator Characteristics1765
- On-Chip Oscillator Characteristics1766
- Subsystem Clock Oscillator Characteristics1767
- PLL Circuit Characteristics1768
- DC Characteristics1769
- Supply Current Characteristics1775
- AC Characteristics1780
- Peripheral Functions Characteristics1783
- Serial Interface IICA1802
- On-Chip Debug (UART)1803
- Analog Characteristics1804
- Temperatures Sensor Characteristics1808
- POR Circuit Characteristics1809
- LVD Circuit Characteristics1810
- Power Supply Voltage Rising Time1811
- Flash Memory Programming Characteristics1812
Chapter 36 Electrical Specifications (Grade Y)1813
- Absolute Maximum Ratings1814
- Oscillator Characteristics1816
- On-Chip Oscillator Characteristics1817
- Subsystem Clock Oscillator Characteristics1818
- PLL Circuit Characteristics1819
- DC Characteristics1820
- Supply Current Characteristics1826
- AC Characteristics1831
- Peripheral Functions Characteristics1834
- Serial Interface IICA1853
- On-Chip Debug (UART)1854
- Analog Characteristics1855
- Temperatures Sensor Characteristics1859
- POR Circuit Characteristics1860
- LVD Circuit Characteristics1861
- Power Supply Voltage Rising Time1862
- Flash Memory Programming Characteristics1863
Appendix A Related Products1872

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