Renesas RL78/F13

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1149
Dec 10, 2015
(13) LIN Interrupt Enable Register (LIEn)
Address: F06CCH
7 6 5 4 3 2 1 0
— — — — SHIE ERRIE FRCIE FTCIE
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
0 FTCIE Successful Frame/Wake-up
Transmission Interrupt Enable
0: Disables successful response/wake-up transmission
interrupt.
1: Enables successful response/wake-up transmission
interrupt.
R/W
1 FRCIE Successful Frame/Wake-up
Reception Interrupt Enable
0: Disables successful response/wake-up reception interrupt.
1: Enables successful response/wake-up reception interrupt.
R/W
2 ERRIE Error Detection Interrupt Enable 0: Disables error detection interrupt.
1: Enables error detection interrupt.
R/W
3 SHIE Successful Header Reception
Interrupt Enable
0: Disables successful header reception interrupt.
1: Enables successful header reception interrupt.
R/W
7 to 4 — Reserved These bits are always read as 0. The write value should
always be 0.
R/W
Set the LIEn register when the OMM0 bit in the LMSTn register is 0 (LIN reset mode).
FTCIE bit (successful frame/wake-up transmission interrupt enable bit)
The FTCIE bit enables or disables interrupt generation upon successful transmission of a response or a wake-up signal.
With 0 set, the interrupt is not generated when the FTC flag in the LSTn register is set to 1.
With 1 set, the interrupt is generated when the FTC flag in the LSTn register is set to 1.
FRCIE bit (successful frame/wake-up reception interrupt enable bit)
The FRCIE bit enables or disables interrupt generation upon successful reception of a response or a wake-up signal
(counting of low width of the input signal).
With 0 set, the interrupt is not generated when the FRC flag in the LSTn register is set to 1.
With 1 set, the interrupt is generated when the FRC flag in the LSTn register is set to 1.
ERRIE bit (error detection interrupt enable bit)
The ERRIE bit enables or disables interrupt generation upon detection of an error.
With 0 set, the interrupt is not generated when the ERR flag in the LSTn register is set to 1.
With 1 set, the interrupt is generated when the ERR flag in the LSTn register is set to 1.
Interrupt sources can be the bit error, frame/response timeout error, framing error, sync field error, checksum error, ID parity
error, and response preparation error.
Detection of the bit error, frame/response timeout error, framing error, sync field error, and ID parity error can be enabled or
disabled using the LEDEn register.
SHIE bit (successful header reception interrupt enable bit)
The SHIE bit enables or disables interrupt generation upon successful transmission of a header.
With 0 set, the interrupt is not generated when the HTRC flag in the LSTn register is set to 1.
With 1 set, the interrupt is generated when the HTRC flag in the LSTn register is set to 1.