RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1269
Dec 10, 2015
Table 18-3. List of CAN Module Registers (7/22)
Address Special Function Register (SFR) Name Symbol R/W Access Size After
Reset
1 bit 8 bits 16 bits
F03EEH CAN receive buffer register 4DH
Note 2
RMDF34L RMDF34 R/W — √ √ 0000H
F03EFH RMDF34H — √
F03F0H CAN receive rule entry register 6CL
Note 1
GAFLPL6L GAFLPL6 R/W — √ √ 0000H
F03F1H GAFLPL6H — √
F03F0H CAN receive buffer register 5AL
Note 2
RMIDL5L RMIDL5 R — √ √ 0000H
F03F1H RMIDL5H — √
F03F2H CAN receive rule entry register 6CH
Note 1
GAFLPH6L GAFLPH6 R/W — √ √ 0000H
F03F3H GAFLPH6H — √
F03F2H CAN receive buffer register 5AH
Note 2
RMIDH5L RMIDH5 R — √ √ 0000H
F03F3H RMIDH5H — √
F03F4H CAN receive rule entry register 7AL
Note 1
GAFLIDL7L GAFLIDL7 R/W — √ √ 0000H
F03F5H GAFLIDL7H — √
F03F4H CAN receive buffer register 5BL
Note 2
RMTS5L RMTS5 R — √ √ 0000H
F03F5H RMTS5H — √
F03F6H CAN receive rule entry register 7AH
Note 1
GAFLIDH7L GAFLIDH7 R/W — √ √ 0000H
F03F7H GAFLIDH7H — √
F03F6H CAN receive buffer register 5BH
Note 2
RMPTR5L RMPTR5 R — √ √ 0000H
F03F7H RMPTR5H — √
F03F8H CAN receive rule entry register 7BL
Note 1
GAFLML7L GAFLML7 R/W — √ √ 0000H
F03F9H GAFLML7H — √
F03F8H CAN receive buffer register 5CL
Note 2
RMDF05L RMDF05 R — √ √ 0000H
F03F9H RMDF05H — √
F03FAH CAN receive rule entry register 7BH
Note 1
GAFLMH7L GAFLMH7 R/W — √ √ 0000H
F03FBH GAFLMH7H — √
F03FAH CAN receive buffer register 5CH
Note 2
RMDF15L RMDF15 R — √ √ 0000H
F03FBH RMDF15H — √
F03FCH CAN receive rule entry register 7CL
Note 1
GAFLPL7L GAFLPL7 R/W — √ √ 0000H
F03FDH GAFLPL7H — √
F03FCH CAN receive buffer register 5DL
Note 2
RMDF25L RMDF25 R — √ √ 0000H
F03FDH RMDF25H — √
F03FEH CAN receive rule entry register 7CH
Note 1
GAFLPH7L GAFLPH7 R/W — √ √ 0000H
F03FFH GAFLPH7H — √
F03FEH CAN receive buffer register 5DH
Note 2
RMDF35L RMDF35 R — √ √ 0000H
F03FFH RMDF35H — √
F0400H CAN receive rule entry register 8AL
Note 1
GAFLIDL8L GAFLIDL8 R/W — √ √ 0000H
F0401H GAFLIDL8H — √
F0400H CAN receive buffer register 6AL
Note 2
RMIDL6L RMIDL6 R — √ √ 0000H
F0401H RMIDL6H — √
F0402H CAN receive rule entry register 8AH
Note 1
GAFLIDH8L GAFLIDH8 R/W — √ √ 0000H
F0403H GAFLIDH8H — √
F0402H CAN receive buffer register 6AH
Note 2
RMIDH6L RMIDH6 R — √ √ 0000H
F0403H RMIDH6H — √
Notes 1. These registers are allocated to RAM window 0 for the CAN module (receive rules and CAN RAM test
register). When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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