RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1270
Dec 10, 2015
Table 18-3. List of CAN Module Registers (8/22)
Address Special Function Register (SFR) Name Symbol R/W Access Size After
Reset
1 bit 8 bits 16 bits
F0404H CAN receive rule entry register 8BL
Note 1
GAFLML8L GAFLML8 R/W — √ √ 0000H
F0405H GAFLML8H — √
F0404H CAN receive buffer register 6BL
Note 2
RMTS6L RMTS6 R — √ √ 0000H
F0405H RMTS6H — √
F0406H CAN receive rule entry register 8BH
Note 1
GAFLMH8L GAFLMH8 R/W — √ √ 0000H
F0407H GAFLMH8H — √
F0406H CAN receive buffer register 6BH
Note 2
RMPTR6L RMPTR6 R — √ √ 0000H
F0407H RMPTR6H — √
F0408H CAN receive rule entry register 8CL
Note 1
GAFLPL8L GAFLPL8 R/W — √ √ 0000H
F0409H GAFLPL8H — √
F0408H CAN receive buffer register 6CL
Note 2
RMDF06L RMDF06 R — √ √ 0000H
F0409H RMDF06H — √
F040AH CAN receive rule entry register 8CH
Note 1
GAFLPH8L GAFLPH8 R/W — √ √ 0000H
F040BH GAFLPH8H — √
F040AH CAN receive buffer register 6CH
Note 2
RMDF16L RMDF16 R — √ √ 0000H
F040BH RMDF16H — √
F040CH CAN receive rule entry register 9AL
Note 1
GAFLIDL9L GAFLIDL9 R/W — √ √ 0000H
F040DH GAFLIDL9H — √
F040CH CAN receive buffer register 6DL
Note 2
RMDF26L RMDF26 R — √ √ 0000H
F040DH RMDF26H — √
F040EH CAN receive rule entry register 9AH
Note 1
GAFLIDH9L GAFLIDH9 R/W — √ √ 0000H
F040FH GAFLIDH9H — √
F040EH CAN receive buffer register 6DH
Note 2
RMDF36L RMDF36 R — √ √ 0000H
F040FH RMDF36H — √
F0410H CAN receive rule entry register 9BL
Note 1
GAFLML9L GAFLML9 R/W — √ √ 0000H
F0411H GAFLML9H — √
F0410H CAN receive buffer register 7AL
Note 2
RMIDL7L RMIDL7 R — √ √ 0000H
F0411H RMIDL7H — √
F0412H CAN receive rule entry register 9BH
Note 1
GAFLMH9L GAFLMH9 R/W — √ √ 0000H
F0413H GAFLMH9H — √
F0412H CAN receive buffer register 7AH
Note 2
RMIDH7L RMIDH7 R — √ √ 0000H
F0413H RMIDH7H — √
F0414H CAN receive rule entry register 9CL
Note 1
GAFLPL9L GAFLPL9 R/W — √ √ 0000H
F0415H GAFLPL9H — √
F0414H CAN receive buffer register 7BL
Note 2
RMTS7L RMTS7 R — √ √ 0000H
F0415H RMTS7H — √
F0416H CAN receive rule entry register 9CH
Note 1
GAFLPH9L GAFLPH9 R/W — √ √ 0000H
F0417H GAFLPH9H — √
F0416H CAN receive buffer register 7BH
Note 2
RMPTR7L RMPTR7 R — √ √ 0000H
F0417H RMPTR7H — √
F0418H CAN receive rule entry register 10AL
Note 1
GAFLIDL10L GAFLIDL10 R/W — √ √ 0000H
F0419H GAFLIDL10H — √
Notes 1. These registers are allocated to RAM window 0 for the CAN module (receive rules and CAN RAM test
register). When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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