RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1300
Dec 10, 2015
• DCS Bit
When this bit is set to 0, the clock obtained by frequency-dividing fCLK by 2 (fCLK/2) is used as the clock source of
the CAN clock (f
CAN).
When this bit is set to 1, the X1 clock (fx) is used as the clock source of the CAN clock. If the X1 clock (fx) is
selected, make the X1 clock (fx) into the value below half
Note1, 2
of fCLK.
Notes 1. When the f
CLK clock source is high-speed on-chip oscillator or PLL clock sourced high-speed on-chip
oscillator, the frequency must be set as “fX < fCLK/2”.
2. If the high-speed system clock is to be selected as f
CLK, do not select fX as fCAN.
• MME Bit
Setting this bit to 1 makes the mirror function available.
• DRE Bit
When the DRE bit is set to 1, the DLC value of the receive rule is stored in the buffer instead of the DLC value
of the received message after the DLC value has passed through the DLC filter. In this case, a value of H'00 is
stored in the data byte that exceeds the DLC value of the receive rule.
When the DCE bit is set to 1 (DLC check is enabled), the DLC replacement function is available.
• DCE Bit
Setting this bit to 1 makes the DLC check function available. Set the GAFLDLC[3:0] bits in the GAFLPHj register
to B'0000 before clearing the DCE bit in the GCFGL register to 0.
• TPRI Bit
This bit is used to set the transmit priority.
When this bit is set to 0, ID priority is selected and the transmit priority complies with the CAN bus arbitration
rule (ISO11898-1 specifications). When this bit is set to 1, transmit buffer number priority is selected and the
minimum number of transmit buffer specified for transmission takes precedence.
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