RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1381
Dec 10, 2015
Table 18-6 shows the global mode transition time.
Table 18-6. Global Mode Transition Time
Mode before Transition Mode after Transition Maximum Transition Time
Global stop Global reset 3 fCLK cycles
Global reset Global stop 3 fCLK cycles
Global reset Global test 10 fCLK cycles
Global reset Global operating 10 fCLK cycles
Global test Global reset 3 fCLK cycles
Global test Global operating 3 fCLK cycles
Global operating Global reset 3 fCLK cycles
Global operating Global test Two CAN frames
(1) Global Stop Mode
In global stop mode, clocks of the CAN do not run and therefore power consumption is reduced. CAN registers can be
read, but writing data to them is prohibited. Register values are retained.
After the operation of the CAN module is enabled, the CAN module transitions to global stop mode. Setting the GSLPR
bit in the GCTRL register to 1 (in global stop mode) in global reset mode sets the CSLPR bit in each of the CiCTRL
register to 1 (channel stop mode). If all channels are forcibly caused to transition to channel stop mode, the CAN module
transitions to global stop mode. The GSLPR bit should not be modified in global operating mode and global test mode.
(2) Global Reset Mode
In global reset mode, CAN module settings are performed. When the CAN module transitions to global reset mode,
some registers are initialized. Table 18-9 and Table 18-10 list the registers to be initialized.
Setting the GMDC[1:0] bits in the GCTRL register to B'01 sets the CHMDC[1:0] bits in each of the CiCTRL register to
B'01 (channel reset mode). If all channels are forcibly caused to transition to channel reset mode, the CAN module
transitions to global reset mode. Channels that are already in channel reset mode or channel stop mode do not transition
(because the CHMDC[1:0] bits have already been set to B'01).
(3) Global Test Mode
In global test mode, settings for test-related registers are performed. When the CAN module transitions to global test
mode, all CAN communications are disabled.
Setting the GMDC[1:0] bits in the GCTRL register to B'10 sets the CHMDC[1:0] bits in each of the CiCTRL register to
B'10 (channel halt mode). If all channels are forcibly caused to transition to channel halt mode, the CAN module transitions
to global test mode. Channels that are in channel stop mode, channel reset mode, or channel halt mode do not transition.
(4) Global Operating Mode
In global operating mode, entire CAN module operates.
When the GMDC[1:0] bits in the GCTRL register are set to B'00, the CAN module transitions to global operating mode.
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