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Renesas RL78/F13 User Manual

Renesas RL78/F13
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RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1417
Dec 10, 2015
(1) When the TMTR bit in the TMCa register is set to 1 while the CAN bus is idle, the transmit priority determination
processing starts to determine the highest-priority transmit buffer. If transmit buffer a is determined to be the
highest-priority transmit buffer, the TMTSTS flag in the corresponding TMSTSa register is set to 1 (transmission is in
progress) and the CAN channel starts transmitting data.
(2) When it is determined that the transmit buffer is used for the next transmission or transmission is in progress,
message transmission is not aborted unless an error or arbitration lost occurs even if the TMTAR bit is set to 1
(transmit abort is requested).
(3) The priority determination starts with the CRC delimiter for the next transmission. In this timing chart, buffer b is not
selected as the next transmit buffer.
(4) When transmit completes successfully, the TMTRF[1:0] flag in the TMSTSa register is set to B'11 (transmission has
been completed (with transmit abort request)), the TMTSTS flag and the TMTR bit in the TMCa register are cleared
to 0, and the TMTCSTSa bit in the TMTCSTS register is set to 1. When the TMIEa value in the TMIEC register is 1
(transmit buffer interrupt is enabled), a CANi transmit interrupt request is generated. To clear the interrupt request,
set the TMTRF[1:0] flag to B'00 (transmission is in progress or no transmit request is present).
(5) While another CAN node is transmitting data on the CAN bus (TMTSTS flag = 0), if the TMTAR bit is set to 1 while
the corresponding channel is determining transmit priority, the TMTR bit cannot be cleared to 0.
(6) After the internal processing time has passed, the transmission is terminated and the TMTRF[1:0] flag is set to B'01
and the TMTASTSb bit in the TMTASTS register is set to 1. When the transmit buffer is not transmitting data and is
not selected as the next transmit buffer and priority determination is not being made, an abort request is immediately
accepted and the TMTRF[1:0] flag is set to B'01. At this time, the TMTR and TMTAR bits are cleared to 0. When
transmit abort is completed with the TAIE bit in the CiCTRH register set to 1 (transmit abort interrupt is enabled), an
interrupt request is generated. To clear the interrupt request, set the TMTRF[1:0] flag to B'00.
If an arbitration lost has occurred after the CAN channel started transmission, the TMTSTS bit is cleared to 0. The
transmit priority determination is reexecuted at the beginning of the CRC delimiter to search the highest-priority transmit
buffer. If an error has occurred during transmission or after arbitration lost, the priority determination processing is
reexecuted during transmission of an error frame.

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Renesas RL78/F13 Specifications

General IconGeneral
BrandRenesas
ModelRL78/F13
CategoryComputer Hardware
LanguageEnglish

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