RL78/F13, F14 CHAPTER 33 INSTRUCTION SET
R01UH0368EJ0210 Rev.2.10 1673
Dec 10, 2015
Table 33-5. Operation List (13/18)
Notes 1. Number of CPU clocks (f
CLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (f
CLK) when the program memory area is accessed.
Remarks 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
2. cnt indicates the bit shift count.
Instruction
Group
Mnemonic Operands Bytes Clocks Clocks Flag
Note 1 Note 2 Z AC CY
Increment/
decrement
INC r 1 1
r r+1 × ×
!addr16 3 2
(addr16) (addr16)+1 × ×
ES:!addr16 4 3
(ES, addr16) (ES, addr16)+1 × ×
saddr 2 2
(saddr) (saddr)+1 × ×
[HL+byte] 3 2
(HL+byte) (HL+byte)+1 × ×
ES: [HL+byte] 4 3
((ES:HL)+byte) ((ES:HL)+byte)+1 × ×
DEC r 1 1
r r – 1 × ×
!addr16 3 2
(addr16) (addr16) – 1 × ×
ES:!addr16 4 3
(ES, addr16) (ES, addr16) – 1 × ×
saddr 2 2
(saddr) (saddr) – 1 × ×
[HL+byte] 3 2
(HL+byte) (HL+byte) – 1 × ×
ES: [HL+byte] 4 3
((ES:HL)+byte) ((ES:HL)+byte) – 1 × ×
INCW rp 1 1
rp rp+1
!addr16 3 2
(addr16) (addr16)+1
ES:!addr16 4 3
(ES, addr16) (ES, addr16)+1
saddrp 2 2
(saddrp) (saddrp)+1
[HL+byte] 3 2
(HL+byte) (HL+byte)+1
ES: [HL+byte] 4 3
((ES:HL)+byte) ((ES:HL)+byte)+1
DECW rp 1 1
rp rp – 1
!addr16 3 2
(addr16) (addr16) – 1
ES:!addr16 4 3
(ES, addr16) (ES, addr16) – 1
saddrp 2 2
(saddrp) (saddrp) – 1
[HL+byte] 3 2
(HL+byte) (HL+byte) – 1
ES: [HL+byte] 4 3
((ES:HL)+byte) ((ES:HL)+byte) – 1
Shift SHR A, cnt 2 1
(CY A0, Am-1 Am
,
A7 0) ×cnt ×
SHRW AX, cnt 2 1
(CY AX0, AXm-1 AXm, AX15 0) ×cnt ×
SHL A, cnt 2 1
(CY A7, Am Am-1, A0 0) ×cnt ×
B, cnt 2 1
(CY B7, Bm Bm-1, B0 0) ×cnt ×
C, cnt 2 1
(CY C7, Cm Cm-1, C0 0) ×cnt ×
SHLW AX, cnt 2 1
(CY AX15, AXm AXm-1, AX0 0) ×cnt ×
BC, cnt 2 1
(CY BC15, BCm BCm-1, BC0 0) ×cnt ×
SAR A, cnt 2 1
(CY A0, Am-1 Am, A7 A7) ×cnt ×
SARW AX, cnt 2 1
(CY AX0, AXm-1 AXm, AX15 AX15) ×cnt ×
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