Renesas RL78/F13

RL78/F13, F14 CHAPTER 33 INSTRUCTION SET
R01UH0368EJ0210 Rev.2.10 1674
Dec 10, 2015
Table 33-5. Operation List (14/18)
Notes 1. Number of CPU clocks (f
CLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (f
CLK) when the program memory area is accessed.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from
the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Instruction
Group
Mnemonic Operands Bytes Clocks Clocks Flag
Note 1 Note 2 Z AC CY
Rotate ROR A, 1 2 1

(CY, A7  A0, Am-1  Am)×1 ×
ROL A, 1 2 1

(CY, A0  A7, Am+1  Am)×1 ×
RORC A, 1 2 1

(CY  A0, A7  CY, Am-1  Am)×1 ×
ROLC A, 1 2 1

(CY  A7, A0  CY, Am+1  Am)×1 ×
ROLWC AX,1 2 1

(CY  AX15, AX0  CY, AXm+1  AXm) ×1 ×
BC,1 2 1

(CY  BC15, BC0  CY, BCm+1  BCm) ×1 ×
Bit
manipulate
MOV1 CY, A.bit 2 1

CY  A.bit ×
A.bit, CY 2 1

A.bit  CY
CY, PSW.bit 3 1

CY  PSW.bit ×
PSW.bit, CY 3 4

PSW.bit  CY × ×
CY, saddr.bit 3 1

CY  (saddr).bit ×
saddr.bit, CY 3 2

(saddr).bit  CY
CY, sfr.bit 3 1

CY  sfr.bit ×
sfr.bit, CY 3 2

sfr.bit  CY
CY,[HL].bit 2 1 4 CY  (HL).bit ×
[HL].bit, CY 2 2

(HL).bit  CY
CY, ES:[HL].bit 3 2 5 CY  (ES, HL).bit ×
ES:[HL].bit, CY 3 3

(ES, HL).bit  CY
AND1 CY, A.bit 2 1

CY  CY  A.bit ×
CY, PSW.bit 3 1

CY  CY  PSW.bit ×
CY, saddr.bit 3 1

CY  CY  (saddr).bit ×
CY, sfr.bit 3 1

CY  CY  sfr.bit ×
CY,[HL].bit 2 1 4 CY  CY  (HL).bit ×
CY, ES:[HL].bit 3 2 5 CY  CY  (ES, HL).bit ×
OR1 CY, A.bit 2 1

CY  CY  A.bit ×
CY, PSW.bit 3 1

CYX  CY  PSW.bit ×
CY, saddr.bit 3 1

CY  CY  (saddr).bit ×
CY, sfr.bit 3 1

CY  CY  sfr.bit ×
CY, [HL].bit 2 1 4 CY  CY  (HL).bit ×
CY, ES:[HL].bit 3 2 5 CY  CY  (ES, HL).bit ×