Renesas RL78/F13 - Page 190

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 158
Dec 10, 2015
Table 3-6. Extended SFR (2nd SFR) List (7/32)
Address Special Function Register (2nd SFR) Name Symbol R/W Manipulable Bit Range After reset
1-bit 8-bit 16-bit
F01F0H Timer channel enable status register 1 TE1L TE1 R    0000H
F01F1H – – –
F01F2H Timer channel start register 1 TS1L TS1 R/W    0000H
F01F3H – – –
F01F4H Timer channel stop register 1 TT1L TT1 R/W    0000H
F01F5H – – –
F01F6H Timer clock select register 1 TPS1 R/W – –  0000H
F01F7H
F01F8H Timer output register 1 TO1L TO1 R/W –   0000H
F01F9H – – –
F01FAH Timer output enable register 1 TOE1L TOE1 R/W    0000H
F01FBH – – –
F01FCH Timer output level register 1 TOL1L TOL1 R/W –   0000H
F01FDH – – –
F01FEH Timer output mode register 1 TOM1L TOM1 R/W –   0000H
F01FFH – – –
F0200H Error address storage register ERADR R – –  0000H
F0201H
F0202H 1-bit error detection interrupt enable register ECCIER R/W –  – 00H
F0203H Bit error detection register ECCER R/W –  – 00H
F0204H ECC test protect register ECCTPR R/W –  – 00H
F0205H ECC test mode register ECCTMDR R/W –  – 00H
F0206H Write data inversion register ECCDWRVR R/W – –  0000H
F0207H
F0220H Port output slew rate select register PSRSEL R/W   – 00H
F0222H SNOOZE status output control register 0 PSNZCNT0 R/W   – 00H
F0223H SNOOZE status output control register 1 PSNZCNT1 R/W   – 00H
F0224H SNOOZE status output control register 2 PSNZCNT2 R/W   – 00H
F0225H SNOOZE status output control register 3 PSNZCNT3 R/W   – 00H
F0227H D/A converter mode register 2 DAM2 R/W   – 00H
F0228H PWM output delay control register 0 PWMDLY0 R/W – –  0000H
F0229H
F022AH PWM output delay control register 1 PWMDLY1 R/W – –  0000H
F022BH
F022CH PWM output delay control register 2 PWMDLY2 R/W – –  0000H
F022DH
F0230H IICA control register 00 IICCTL00 R/W   – 00H
F0231H IICA control register 01 IICCTL01 R/W   – 00H
F0232H IICA low-level width setting register 0 IICWL0 R/W –  – FFH
F0233H IICA high-level width setting register 1 IICWH0 R/W –  – FFH
F0234H Slave address register 0 SVA0 R/W –  – 00H