RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 411
Dec 10, 2015
(7) Change the CPU from operating with the subsystem clock (D) or operating with the low-speed on-chip
oscillator clock (M) to operating with the high-speed on-chip oscillator clock (B).
Set the HIOSTOP bit of the CSC register to 0.
Note
Set the CSS bit of the CKC register to 0.
Confirm that the CLS bit of the CKC register is set to 0.
Note When oscillation starts from a high-speed on-chip oscillator clock stop state (HIOSTOP = 1), have the software
wait for the following oscillation accuracy stabilization time, and then change the clock.
FRQSEL4 of the user option byte (000C2H/020C2H) = 0: 18 s to 65 s
FRQSEL4 of the user option byte (000C2H/020C2H) = 1: 18 s to 105 s
(8) Change the CPU from operating with the PLL clock (K) to operating with the high-speed system clock (C) or
operating with the high-speed on-chip oscillator clock (B).
Set the SELPLL bit of the PLLCTL register to 0.
Confirm that the SELPLLS bit of the PLLSTS register is set to 0.
(9) Change the CPU from operating with the subsystem clock (D) or operating with the low-speed on-chip
oscillator clock (M) to operating with the high-speed system clock (C).
Set the CMC register (EXCLK = 0, OSCSEL = 1, AMPH = x).
Note 1
Set the OSTS register.
Note 2
Check the oscillation stabilization time by using the OSTC register.
Note 2
Set the CSS bit of the CKC register to 0.
Confirm that the CLS bit of the CKC register is set to 0.
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
2. Set the oscillation stabilization time of the oscillation stabilization time select register (OSTS) as shown below:
OSTS register setting value > Expected oscillation stabilization time counter status register (OSTC)
(10) Change the CPU from each operation mode to HALT mode.
The CPU changes from operating with the high-speed on-chip oscillator clock (B) to HALT mode (E).
The CPU changes from operating with the high-speed system clock (C) to HALT mode (F).
The CPU changes from operating with the subsystem clock (D) to HALT mode (G).
The CPU changes from operating with the PLL clock (K) to HALT mode (L).
The CPU changes from operating with the low-speed on-chip oscillator clock (M) to HALT mode (N).
- Execute the HALT instruction.
(11) The CPU changes from operating with the high-speed on-chip oscillator clock (B) to STOP mode (H).
Stop peripheral functions that are not operated in STOP mode.
Execute the STOP instruction.
(12) The CPU changes from operating with the high-speed system clock (C) to STOP mode (I).
Stop peripheral functions that are not operated in STOP mode.
Set the OSTS register.
Note
Execute the STOP instruction.
Note Set the oscillation stabilization time of the oscillation stabilization time select register (OSTS) as shown below:
OSTS register setting value > Expected oscillation stabilization time counter status register (OSTC)
(13) Change the CPU from STOP mode (H) to SNOOZE mode (J).
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