RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 625
Dec 10, 2015
Table 8-14. Input Capture Function Specifications
Item Specification
Count sources
Note 1
fCLK, fPLL, fIH, fSUB, fPL
External signal input to the TRDCLK0 pin (active edge selected by a program)
Count operations Increment
Count period When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000B (free-
running operation).
1/fk × 65536 fk: Frequency of count source
Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop condition 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi
bit in the TRDSTR register is set to 1.
Interrupt request generation timing • Input capture (active edge of TRDIOji input)
• TRDi register overflow
TRDIOA0 pin function I/O port, input-capture input, or TRDCLK (external clock) input
TRDIOB0, TRDIOC0, TRDIOD0,
TRDIOA1 to TRDIOD1 pin function
I/O port or input-capture input (selectable for each pin)
INTP0 pin function Not used (port or INTP0 interrupt input)
Read from timer The count value can be read by reading the TRDi register.
Write to timer • When the TRDSYNC bit in the TRDMR register is 0 (timer RD0 and timer RD1
operate independently).
Data can be written to the TRDi register.
• When the TRDSYNC bit in the TRDMR register is 1 (timer RD0 and timer RD1
operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi
register.
Selectable functions • Input-capture input pin selection
Either one pin or multiple pins of TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi.
• Input-capture input active edge selection
Rising edge, falling edge, or both rising and falling edges
• Timing for setting the TRDi register to 0000H.
At overflow or input capture
• Buffer operation (see 8. 3. 1 (2) Buffer Operation)
• Synchronous operation (see 8. 3. 1 (3) Synchronous Operation)
• Digital filter.
The TRDIOji input is sampled, and when the sampled input level match three
times, that level is determined.
• Input capture operation by event input from event link controller (ELC).
Note 2
Notes 1. When selecting the count source for the timer RD, set the same clock source as the count source for fCLK
before setting bit 4 (TRD0EN) in the peripheral enable register 1 (PER1).
2. The ELC is only available in the RL78/F14.
Remark i = 0 or 1, j = A, B, C, or D
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