330Tibbo Project System (TPS)
© Tibbo Technology Inc.
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Set the SCLK line HIGH. Now the FPGA is out of reset.
If the above sounds cryptic, here is the schematic diagram of the reset circuit:
The circuit is based on a D trigger that is clocked by the SCLK line. The data input D
of the trigger is connected to the -CS line. The FPGA's reset line (active LOW) is
taken from the inverted output -Q of the trigger. Setting the -CS line HIGH and
producing a rising edge on the SCLK line latches the trigger, and its -Q (inverted)
output becomes LOW. The FPGA IC enters the reset state. To release the FPGA
from reset, you need to set the -CS line LOW and produce another rising edge on
the SCLK line.
Once the FPGA is out of reset, avoid toggling the SCLK line while the -CS is HIGH
(inactive). This shouldn't be problematic as there is no point in generating SPI
clocks while the chip select is not asserted.
Following reset, the FPGA must be uploaded with the run-time binary file (for
reference, see tbt26_init() @ tbt26.tbs of the test_tibbit_26 project).
Key points:
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SPI mode 2 is used; bytes are transmitted MSBit first.
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Bytes of the run-time binary (IR_Remote_bitmap.bin) are sent to the FPGA one
after one.
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After the last byte has been sent, the program generates 50 additional clock
cycles. We don't know why this is necessary. We just followed Lattice
specification.
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After that, the success or failure of the upload procedure are verified through the
DONE/MISO line.
As the name implies, the DONE/MISO line serves two functions. When the -CS is
asserted (LOW), this line works as the standard MISO line of the SPI interface.
When the -CS line is HIGH, this line channels the state of the FPGA's CDONE output.
This output becomes HIGH if the upload of the binary file was successful.
SPI Read and Write Transactions
As with all SPI communications, transactions start when the -CS line goes LOW and
end when the -CS line goes HIGH.
SPI write transaction
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