Xilinx Virtex-5 RocketIO GTP

292 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Appendix D: DRP Address Map of the GTP_DUAL Tile
R
RX_BUFFER_USE_0
42<3>
RX_BUFFER_USE_1
0d<12>
RX_DECODE_SEQ_MATCH_0
42<2>
RX_DECODE_SEQ_MATCH_1
0d<13>
RX_LOS_INVALID_INCR_0
41<15>
42<0> 42<1>
RX_LOS_INVALID_INCR_1
0e<0>
0d<15> 0d<14>
RX_LOS_THRESHOLD_0
41<11>
41<12> 41<13>
RX_LOS_THRESHOLD_1
0e<4> 0e<3> 0e<2>
RX_LOSS_OF_SYNC_FSM_0
41<14>
RX_LOSS_OF_SYNC_FSM_1
0e<1>
RX_SLIDE_MODE_0
41<10>
RX_SLIDE_MODE_1
0e<5>
RX_STATUS_FMT_0
41<9>
Table D-2: DRP Address by Attribute (Continued)
Attribute
Bit
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31