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Xilinx Virtex-5 RocketIO GTP User Manual

Xilinx Virtex-5 RocketIO GTP
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136 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 7: GTP Receiver (RX)
R
RX Clock Data Recovery (CDR)
Overview
The RX Clock Data Recovery (CDR) circuit in each GTP transceiver extracts a recovered
clock from incoming data. As long as the line rate of the recovered clock matches the line
rate of the receiver within 350 ppm and there are sufficient transitions in the data, the CDR
can extract a clock. The CDR has advanced features, including a scanning feature that can
be used to evaluate the quality of the received signal.
Ports and Attributes
Table 7-9 defines RX CDR signaling ports.
Table 7-9: RX CDR Signaling Ports
Port Dir Clock Domain Description
RESETDONE0
RESETDONE1
Out Async
This port goes High when the GTP transceiver has finished
reset and is ready for use. For this signal to work correctly,
CLKIN and all clock inputs on the individual GTP transceiver
(TXUSRCLK, TXUSRCLK2, RXUSRCLK, RXUSRCLK2) must
be driven.
RXCDRRESET0
RXCDRRESET1
In RXUSRCLK2
Individual reset signal for the RX CDR and the RX part of the
PCS for this channel. This signal is driven High to cause the
CDR to give up its current lock and return to the shared PLL
frequency.
RXELECIDLERESET In Async
This port is required to hold the CDR in reset while the
receiver is in electrical idle. This functionality is required
when using OOB signaling and also during start-up when
transients might temporarily put the CDR in the electrical idle
state. The “RX Clock Data Recovery (CDR)” section shows
how this port must be connected for all GTP designs.
0: CDR operates normally.
1: CDR held in reset. RXELECIDLERESET must be High
while RXELECIDLE is High during normal operation.
RXENELECIDLERESETB In Async
This port is required to enable the CDR reset function while
the receiver is in electrical idle. This functionality is required
when using OOB signaling and also during start-up when
transients might temporarily put the CDR in the electrical idle
state. The “RX Clock Data Recovery (CDR)” section shows
how this port must be connected for all GTP designs.
0: CDR reset function enabled
1: CDR reset function disabled

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Xilinx Virtex-5 RocketIO GTP Specifications

General IconGeneral
BrandXilinx
ModelVirtex-5 RocketIO GTP
CategoryTransceiver
LanguageEnglish

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