Xilinx Virtex-5 RocketIO GTP User Manual

130 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 7: GTP Receiver (RX)
R
Ports and Attributes
Table 7-5 defines the RX OOB/beacon signaling ports.
Table 7-5: RX OOB/Beacon Signaling Ports
Port Dir Clock Domain Description
RXELECIDLE0
RXELECIDLE1
Out RXUSRCLK2
Indicates the differential voltage between RXN and RXP dropped below
the minimum threshold (OOBDETECT_THRESHOLD). Signals below
this threshold are OOB signals.
1: OOB signal detected. The differential voltage is below the minimum
threshold.
0: OOB signal not detected. The differential voltage is above the
minimum threshold.
This port is intended for PCI Express and SATA standards.
RXSTATUS0[2:0]
RXSTATUS1[2:0]
Out RXUSRCLK2
The decoding of RXSTATUS[2:0] depends on the setting of
RX_STATUS_FMT.
When RX_STATUS_FMT = PCIE:
000: Receiver not present (when in receiver detection
sequence)/Received data OK (during normal operation)
001: Reserved
010: Reserved
011: Receiver present (when in receiver detection sequence)
100: 8B/10B decode error
101: Elastic Buffer Overflow. Stays asserted until cleared (different
than defined in the PIPE specification).
110: Elastic Buffer Underflow. Stays asserted until cleared (different
than defined in the PIPE specification).
111: Receive Disparity Error
When RX_STATUS_FMT = SATA:
RXSTATUS[0]: TXCOMSTART operation complete
RXSTATUS[1]: COMWAKE signal received
RXSTATUS[2]: COMRESET/COMINIT signal received
RXVALID0
RXVALID1
In RXUSRCLK2
Indicates symbol lock and valid data on RXDATA and RXCHARISK[1:0]
when High, as defined in the PHY Interface for PCI Express (PIPE)
specification.

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English