Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 49
UG196 (v1.3) May 25, 2007
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Chapter 4
Implementation
Overview
This chapter provides the information needed to map GTP_DUAL tiles instantiated in a
design to device resources, including:
• The location of the GTP_DUAL tiles on the available device and package
combinations.
• The pad numbers of external signals associated with each GTP_DUAL tile.
• How GTP_DUAL tiles and clocking resources instantiated in a design are mapped to
available locations with a user constraints file (UCF).
It is a common practice to define the location of GTP transceivers early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis
during board design. The implementation flow facilitates this practice through the use of
location constraints in the UCF.
While this chapter describes how to instantiate GTP_DUAL clocking components, the
details of the different GTP_DUAL tile clocking options are discussed in “Clocking,” page
68.
Ports and Attributes
Table 4-1 shows the external ports associated with each GTP_DUAL tile.
Table 4-1: GTP_DUAL Tile External Ports
Port Dir Domain Description
MGTTXP0
MGTTXN0
MGTTXP1
MGTTXN1
Out
Embedded
TX Clock
Differential transmit data pairs for
GTP transceivers 0 and 1
MGTRXP0
MGTRXN0
MGTRXP1
MGTRXN1
In
Embedded
RX Clock
Differential receive data pairs for GTP
transceivers 0 and 1
MGTREFCLKP
MGTREFCLKN
In N/A Differential reference clock input pair
MGTAVCCPLL
(2)
Analog Analog Pad for 1.2V supply for PLL

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English