Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 315
UG196 (v1.3) May 25, 2007
Example
R
Example
The example system shown in Figure F-2 has six GTP_DUAL tiles with four reference
clocks. It demonstrates several different clocking schemes.
Table F-2 describes the example in Figure F-2. When using the GTP_DUAL tile D, to select
clock 1 as the CLKIN source, set the REFCLK_SEL to 1x1.
Figure F-2: Example System
Table F-2: GTP Tile Utilization
GTP_DUAL
Tile
CLKIN
Options
REFCLK_SEL CLKNORTH_SEL CLKSOUTH_SEL
A
Clock 2 1x1 Don’t Care: Nowhere to
send the northbound
clock.
Don’t Care: No
southbound clock to
forward.
Clock 4 xx0
B
Clock 2 1x1
0: Forward clock 2
northbound to tile A.
1: Drive clock 3
southbound to tile C.
Clock 3 011
GTP_DUAL Tile
Clock
Muxing
BUFG/BUFR
Clock 4 = GREFCLK
IBUFDS
CLKP
CLKIN
GREFCLK
A PLL
GTP
Dedicated
Clock
Routing
CLKN
GTP_DUAL Tile
Clock
Muxing
BUFG/BUFR
IBUFDS
Clock 3
CLKP
CLKIN
GREFCLK
B PLL
GTP
Dedicated
Clock
Routing
CLKN
GTP_DUAL Tile
Clock
Muxing
BUFG/BUFR
IBUFDS
Clock 2
CLKP
CLKIN
GREFCLK
C PLL
GTP
Dedicated
Clock
Routing
CLKN
GTP_DUAL Tile
Clock
Muxing
BUFG/BUFR
IBUFDS
CLKP
CLKIN
GREFCLK
D PLL
GTP
Dedicated
Clock
Routing
CLKN
GTP_DUAL Tile
Clock
Muxing
BUFG/BUFR
IBUFDS
CLKP
CLKIN
GREFCLK
E PLL
GTP
Dedicated
Clock
Routing
CLKN
GTP_DUAL Tile
Clock
Muxing
BUFG/BUFR
IBUFDS
UG196_af_02_042807
Clock 1
CLKP
CLKIN
GREFCLK
F PLL
GTP
Dedicated
Clock
Routing
CLKN

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English