Xilinx Virtex-5 RocketIO GTP User Manual

110 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 6: GTP Transmitter (TX)
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Description
Each GTP transceiver includes a built-in PRBS generator. This feature can be used in
conjunction with other test features, such as loopback and the built-in PRBS checker, to run
tests on a given channel. Only the 10-bit internal data width mode is supported, which
implies that INTDATAWIDTH must also be set to 1 when the PRBS generator is enabled.
To use the PRBS generator, set INTDATAWIDTH to 1 to set the internal datapath width to
10 bits. The PRBS test mode is selected using the TXENPRBSTST port. Table 6-12 lists the
available settings.
Parallel In to Serial Out (PISO)
Overview
The Parallel In, Serial Out (PISO) block is the heart of the GTP TX datapath. It serializes
parallel data from the PCS using a high-speed clock from the shared PMA PLL.
The PISO block serializes eight or ten bits per parallel clock cycle, depending on the
internal data width for the tile (INTDATAWIDTH). The clock rate is determined by the
shared PMA PLL rate, divided by a local TX divider.
Ports and Attributes
Table 6-13 defines the TX PISO ports.
Table 6-13: TX PISO Ports
Port Dir Clock Domain Description
INTDATAWIDTH In Async
Specifies the width of the internal
datapath for the entire GTP_DUAL
tile. This shared port is also described
in “Shared PMA PLL,” page 60.
0: Internal datapath is 8 bits wide
1: Internal datapath is 10 bits wide

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English