Xilinx Virtex-5 RocketIO GTP

52 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 4: Implementation
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Package Placement Information
The diagrams in this section illustrate GTP_DUAL placement for the following packages:
• LXT packages:
♦ XC5VLX30T-FF665
♦ XC5VLX50T-FF665
♦ XC5VLX50T-FF1136
♦ XC5VLX85T-FF1136
♦ XC5VLX110T-FF1136
♦ XC5VLX110T-FF1738
♦ XC5VLX220T-FF1738
♦ XC5VLX330T-FF1738
• SXT packages:
♦ XC5VSX35T-FF665
♦ XC5VSX50T-FF665
♦ XC5VSX50T-FF1136
♦ XC5VSX95T-FF1136
Figure 4-1 illustrates the nomenclature used in each of these diagrams. The GTP_DUAL
placement name is the name used in the UCF to map GTP_DUAL tiles instantiated in the
design to specific tiles on the device. The board-level pin names and numbers are the
names placed in the PKG file generated by the ISE design flow. This file is typically used by
board-level schematic capture and layout tools to create component symbols and layout
footprints.
Figure 4-1: Placement Diagram Nomenclature
MGTAVCCPLL_116
MGTAVCC_116
MGTAVCC_116
F3D4
D3
E3F1
E4E1
C3
C1
D1
B3G2
G3
F2
B2
C2
GTP_DUAL_X0Y3
MGTAVTTTX_116
MGTAVTTTX_116
MGTAVTTRX_116
MGTTXN0_116
MGTTXP0_116
MGTTXN1_116
MGTTXP1_116
MGTRXN0_116
MGTRXP0_116
MGTRXN1_116
MGTRXP1_116
MGTREFCLKP_116
MGTREFCLKN_116
UG196_c4_01_102006
GTP_DUAL
Placement Name
Board-Level
Pin Numbers
Board-Level
Pin Names