Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 59
UG196 (v1.3) May 25, 2007
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Chapter 5
Tile Features
Tile Features Overview
To minimize power consumption and area, many important GTP functions are shared
between two transceivers. These functions include the generation of a high-speed serial
clock, resets, power control, and dynamic reconfiguration.
Correct clocking and reset behavior is critical for any GTP transceiver design. This chapter
describes the following steps that must be performed when configuring the GTP_DUAL
tile:
• Set the shared PLL rate
• Set the reference clock source
• Implement the Link Idle Reset circuit
These steps are performed automatically when the Wizard is used to configure the
GTP_DUAL tile.

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English