Xilinx Virtex-5 RocketIO GTP User Manual

90 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 6: GTP Transmitter (TX)
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FPGA TX Interface
Overview
The FPGA TX interface is the FPGA’s gateway to the TX datapath of the GTP transceiver.
Applications transmit data through the GTP transceiver by writing data to the TXDATA
port on the positive edge of TXUSRCLK2.
The width of the port can be configured to be one or two bytes wide. The actual width of
the port depends on the GTP_DUAL tile's INTDATAWIDTH setting (controls the width of
the internal datapath), and whether or not the 8B/10B encoder is enabled. Port widths can
be 8 bits, 10 bits, 16 bits, and 20 bits.
The rate of the parallel clock (TXUSRCLK2) at the interface is determined by the TX line
rate, the width of the TXDATA port, and whether or not 8B/10B encoding is enabled. A
second parallel clock (TXUSRCLK) must be provided for the internal PCS logic in the
transmitter. This chapter shows how to drive the parallel clocks and explains the
constraints on those clocks for correct operation.
Ports and Attributes
Table 6-1 defines the FPGA TX interface ports.
Table 6-1: FPGA TX Interface Ports
Port Dir Clock Domain Description
INTDATAWIDTH In Async
Specifies the width of the internal datapath for the entire GTP_DUAL
tile. This shared port is also described in “Shared PMA PLL,” page 60.
• 0: Internal datapath is 8 bits wide
• 1: Internal datapath is 10 bits wide
REFCLKOUT Out N/A
The REFCLKOUT port from each GTP_DUAL tile provides direct
access to the reference clock provided to the shared PLL (CLKIN). It
can be routed for use in the FPGA logic.
TXDATA0[15:0]
TXDATA1[15:0]
In TXUSRCLK2
The bus for transmitting data. The width of this port depends on
TXDATAWIDTH:
• TXDATAWIDTH = 0:
TXDATA[7:0] = 8 bits wide
• TXDATAWIDTH = 1:
TXDATA[15:0] = 16 bits wide
When a 10-bit or a 20-bit bus is required, the TXCHARDISPVAL and
TXCHARDISPMODE ports from the 8B/10B encoder are
concatenated with the TXDATA port. See Figure 6-3, page 92.
TXDATAWIDTH0
TXDATAWIDTH1
In TXUSRCLK2
Selects the width of the TXDATA port.
• 0: TXDATA is 8 bits or 10 bits wide
• 1: TXDATA is 16 bits or 20 bits wide
TXENC8B10BUSE In TXUSRCLK2
TXENC8B10BUSE is set High to enable the 8B/10B encoder.
INTDATAWIDTH must also be High.
0: 8B/10B encoder bypassed. This option reduces latency.
1: 8B/10B encoder enabled. INTDATAWIDTH must be 1.

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English