Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 13
UG196 (v1.3) May 25, 2007
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Preface
About This Guide
This document shows how to use the RocketIO™ GTP transceivers in Virtex™-5 FPGAs.
Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on
the Xilinx website at http://www.xilinx.com/virtex5
.
Guide Contents
This manual contains the following chapters and appendices:
• “Section 1: FPGA Level Design”
♦ Chapter 1, “Introduction to the RocketIO GTP Transceiver”
♦ Chapter 2, “RocketIO GTP Transceiver Wizard”
♦ Chapter 3, “Simulation”
♦ Chapter 4, “Implementation”
♦ Chapter 5, “Tile Features”
♦ Chapter 6, “GTP Transmitter (TX)”
♦ Chapter 7, “GTP Receiver (RX)”
♦ Chapter 8, “Cyclic Redundancy Check (CRC)”
♦ Chapter 9, “Loopback”
♦ Chapter 10, “GTP-to-Board Interface”
• “Section 2: Board Level Design”
♦ Chapter 11, “Design Constraints Overview”
♦ Chapter 12, “PCB Materials and Traces”
♦ Chapter 13, “Design of Transitions”
♦ Chapter 14, “Guidelines and Examples”
• “Section 3: Appendices”
♦ Appendix A, “MGT to GTP Transceiver Design Migration”
♦ Appendix B, “OOB/Beacon Signaling”
♦ Appendix C, “8B/10B Valid Characters”
♦ Appendix D, “DRP Address Map of the GTP_DUAL Tile”
♦ Appendix E, “Low Latency Design”

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English