Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 111
UG196 (v1.3) May 25, 2007
Parallel In to Serial Out (PISO)
R
Table 6-14 defines the TX PISO attributes.
Description
Equation 6-3 shows how to calculate the TX line rate when operating without
oversampling (OVERSAMPLE_MODE = FALSE). If PLL_TXDIVSEL_COMM_OUT is
greater than 1, PLL_TXDIVSEL_OUT must be set to 1, and vice versa.
PLL_TXDIVSEL_COMM_OUT should be used when both GTP transceivers in the
GTP_DUAL tile use the same TX line rate.
Equation 6-3
When oversampling is activated, use Equation 6-4 to calculate the line rate.
Equation 6-4
See “Oversampling,” page 143 for more information about oversampling.
Table 6-14: TX PISO Attributes
Attribute Description
OVERSAMPLE_MODE
This shared attribute activates the built-in 5x digital
oversampling circuits in both GTP_DUAL transceivers.
Oversampling must be enabled when running the GTP
transceivers at line rates between 100 Mb/s and 500 Mb/s.
TRUE: Built-in 5x digital oversampling enabled for both
GTP transceivers on the tile
FALSE: Digital oversampling disabled
See “Oversampling,” page 143 for more details about 5x
digital oversampling.
PLL_TXDIVSEL_OUT_0
PLL_TXDIVSEL_OUT_1
Sets the divider for the TX line rate for the individual GTP
transceiver. If PLL_TXDIVSEL_COMM_OUT is greater
than 1, PLL_TXDIVSEL_OUT must be set to 1, and the TX
line rate is set by PLL_TXDIVSEL_COMM_OUT. The
divider can be set to 1, 2, or 4.
PLL_TXDIVSEL_COMM_OUT
Sets a common line rate divider for both GTP transceivers
in a tile. The common divider should be used whenever
both GTP transceivers in a tile use the same line rate
because it reduces skew between lanes.
PLL_TXDIVSEL_OUT must always be set to 1 when
PLL_TXDIVSEL_COMM_OUT is greater than 1. The
divider can be set to 1, 2, or 4.
Tx Line Rate
PLL Clock Rate 2×
PLL_TXDIVSEL_OUT PLL_TXDIVSEL_COMM_OUT×
----------------------------------------------------------------------------------------------------------------------------------------------------=
Tx Line Rate
PLL Clock Rate 2×
PLL_TXDIVSEL_OUT PLL_TXDIVSEL_COMM_OUT× 5×
-------------------------------------------------------------------------------------------------------------------------------------------------------------=

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English