Xilinx Virtex-5 RocketIO GTP

280 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Appendix D: DRP Address Map of the GTP_DUAL Tile
R
OOB_CLK_DIVIDER
1 000
2 001
3 010
4 011
5 100
6 101
10 110
12 111
PLL_DIVSEL_FB
1 10000
2 00000
3 00001
4 00010
5 00110
PLL_DIVSEL_REF
1 010000
2 000000
PLL_RXDIVSEL_OUT
1 00
2 01
4 10
PLL_TXDIVSEL_COMM_OUT
1 00
2 01
4 10
PLL_TXDIVSEL_OUT
1 00
2 01
4 10
RX_LOS_INVALID_INCR
1 000
2 001
4 010
8 011
16 100
32 101
64 110
128 111
Tab le D - 1 : Special Attribute Mappings (Continued)
Attribute UCF/HDL Attribute Value DRP Binary Value