Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 167
UG196 (v1.3) May 25, 2007
Configurable RX Elastic Buffer and Phase Alignment
R
Bypassing the RX Buffer while Using Built-In Oversampling
If OVERSAMPLE_MODE is TRUE to activate built-in oversampling, the RX buffer is
bypassed without the use of phase alignment. Instead, a shallow buffer inside the
Oversampling block is used to resolve phase differences between RXUSRCLK and
RXRECCLK. See “Oversampling,” page 143 for information about monitoring the status of
the Oversampling block.
Figure 7-24 shows how the RX buffer is bypassed with oversampling enabled. The shallow
buffer in the Oversampling block resolves any phase differences between RXUSRCLK and
the recovered clock it generates.
To bypass the RX buffer when OVERSAMPLING_MODE is TRUE:
1. Set RX_BUFFER_USE to FALSE to bypass the RX buffer (optional).
2. Set RX_XCLK_SEL to “RXUSR”.
3. Source RXUSRCLK and RXUSRCLK2 with the RXRECCLK output. Divide
RXRECCLK by 2 if necessary to provide RXUSRCLK2 (see “FPGA RX Interface,” page
182 for details).
Figure 7-24: Buffer Bypass with Oversampling Enabled
RX Serial Clock
RX-PMA RX-PCS
RX
CDR
PMA
PLL
Divider
From PMA PLL
RX
EQ
SIPO
FPGA
Logic
Elastic
Buffer
RX Status Control
10B
/
8B
Loss of Sync
Over-
Sampling
PMA Parallel Clock
(XCLK)
PCS Parallel
Clock
(RXUSRCLK)
RX Interface
Parallel Clock
(RXUSRCLK2)
Polarity
PRBS
Check
RX Pipe Control
RX Buffer Bypassed
Comma
Detect
&
Align
UG196_c7_35_102306
Oversampling block acts as a shallow buffer:
- Resolves phase differences between the Oversampling
block recovered clock and RXUSRCLK
- Cannot resolve frequency differences

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English