Xilinx Virtex-5 RocketIO GTP

66 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 5: Tile Features
R
5. Calculate the required DIV value.
Because the internal datapath with must be eight bits and INTDATAWIDTH = 0,
DIV = 4.
6. Calculate the required PLL divider ratio
Using the values f
CLKIN
, DIV, and f
PLL_CLOCK
determined above, rearrange
Equation 5-1 to calculate the divider ratio as shown in Equation 5-3. The result is a
ratio of two.
Equation 5-3
7. Select the PLL divider values
Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 2 and PLL_DIVSEL_REF = 1 results in a ratio of two.
Configuring the Shared PLL for Gigabit Ethernet
This example shows how to set the shared PLL divider settings for Gigabit Ethernet using
Equation 5-1. The RocketIO GTP Wizard and Table 5-3 are simpler alternatives. This
example is provided only to illustrate the process with Equation 5-1.
Use Equation 5-1 as described in the following steps:
1. Determine the required line rates.
For Gigabit Ethernet, both TX and RX use a line rate of 1.25 Gb/s.
2. Determine the internal datapath width.
Because Gigabit Ethernet uses 8B/10B encoding, an internal datapath width of 10 bits
is required.
3. Determine the desired reference clock rate.
This example uses a reference clock running at 125 MHz.
4. Calculate the required PLL clock rate.
Because the SIPO block uses both edges of the clock to deserialize data, it must be fed
a clock running at 1.25/2 = 0.625 GHz. Because this RX rate of 0.625 GHz is below the
operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be two
to allow the PLL to run twice as fast (1.25 GHz). The PLL clock rate is thus 0.625 x 2 =
1.25 GHz.
5. Calculate the required DIV value.
Because the internal datapath with must be 10 bits and INTDATAWIDTH = 1, DIV = 5.
6. Calculate the required PLL divider ratio.
Using the values f
CLKIN
, DIV, and f
PLL_CLOCK
determined above, rearrange
Equation 5-1 to calculate the divider ratio as shown in Equation 5-4. The result is a
ratio of two.
Equation 5-4
PLL_DIVSEL_FB
PLL_DIVSEL_REF
-----------------------------------------------------
f
PLL_Clock
f
CLKIN
DIV×
-----------------------------------
1.244 GHz
155.5 MHz 4×
--------------------------------------
2===
PLL_DIVSEL_FB
PLL_DIVSEL_REF
-----------------------------------------------------
f
PLL_Clock
f
CLKIN
DIV×
-----------------------------------
1.25 GHz
125 MHz 5×
----------------------------------
2===