Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 63
UG196 (v1.3) May 25, 2007
Shared PMA PLL
R
Table 5-3 shows example settings for several standard protocols. The PLL clock frequency
values shown in Table 5-3 are in the operation range of the shared PLL specified in the
Virtex-5 Data Sheet.
Figure 5-2: Shared PLL Conceptual View
DIV
/[4,5]
UG196_c5_02_041907
PLL_DIVSEL_FB
/[1,2,3,4,5]
Note 1
Phase/
Frequency
Detector
(PFD)
PLL_DIVSEL_REF
/[1,2]
Charge
Pump
Loop
Filter F(s)
VCO
PLL Clock
REFCLKOUT
CLKIN
Notes:
1. When INTDATAWIDTH = 0, PLL_DIVSEL_FB can only be set to 1, 2, or 4.
Table 5-3: Communication Standards
Standard
Line
Rate
[Gb/s]
TX/RX
USRCLK
Frequency
[MHz]
Reference
Clock
Frequency
REFCLK
[MHz]
PLL Clock
Frequency
[GHz]
Reference Clock
Divider Setting
PLL_DIVSEL_REF
Feedback Loop
Divider Setting
PLL_DIVSEL_FB
Divider Settings
PLL_RXDIVSEL_OUT_(0/1)
PLL_TXDIVSEL_OUT_(0/1)
PLL_TXDIVSEL_COMM_OUT
(1)
INTDATAWIDTH = 1 (10-bit internal datapath) → (DIV = 5)
FC2 2.125 212.5 212.5 1.0625 1 1 1
FC1 1.0625 106.25 106.25 1.0625 1 2 2
XAUI 3.125 312.5 156.25 1.5625 1 2 1
10G BASE-CX4 3.125 312.5 156.25 1.5625 1 2 1
GigE 1.25 125 125 1.25 1 2 2
Aurora
3.125 312.5 156.25 1.5625 1 2 1
2.5 250 125 1.25 1 2 1
1.25 125 125 1.25 1 2 2
Serial RapidIO
3.125 312.5 156.25 1.5625 1 2 1
2.5 250 125 1.25 1 2 1
1.25 125 125 1.25 1 2 2
SATA II 3 300 150 1.5 1 2 1
SATA I 1.5 150 150 1.5 1 2 2
SAS II 3 300 150 1.5 1 2 1
SAS I 1.5 150 150 1.5 1 2 2
PCI Express 2.5 250 100 1.25 2 5 1
Infiniband 2.5 250 125 1.25 1 2 1
HD-SDI
(4)
1.485 148.5 148.5 1.485 2 4 2

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English