Xilinx Virtex-5 RocketIO GTP

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 77
UG196 (v1.3) May 25, 2007
Reset
R
Resetting the GTP_DUAL Tile
Each GTP_DUAL tile offers several ways to reset its subcomponents. Table 5-7 shows all
the different ways of resetting a GTP_DUAL tile, and the subcomponents that are affected
by each type of reset.
Table 5-7: Available Resets Pins and the Components Reset by These Reset Pins
Component
Configuration
GTPRESET
PLLPOWERDOWN
(Falling Edge)
TXRESET
RXCDRRESET
RXRESET
RXBUFRESET
RXELECIDLERESET
PRBSCNTRESET
GTP to Board
Interface
Termination Resistor
Calibration
✓
Shared
Resources
Shared PLL ✓✓✓
PLL Lock Detection ✓✓✓
Reset Control ✓✓✓
Power Control ✓✓✓
Clocking ✓✓✓
DRP ✓
TX PCS FPGA TX Interface ✓✓✓✓
8B/10B Encoder ✓✓✓✓
TX Buffer ✓✓✓✓
PRBS Generator ✓✓✓✓
Polarity Control ✓✓✓✓
TX PMA PISO ✓✓✓
TX Pre-emphasis ✓✓✓
TX OOB & PCI ✓✓✓
TX Driver ✓✓✓
RX PCS FPGA RX Interface ✓✓✓ ✓✓
RX Buffer ✓✓✓ ✓✓✓
RX Status Control ✓✓✓ ✓✓
8B/10B Decoder ✓✓✓ ✓✓
Comma Detect and Align ✓✓✓ ✓✓
RX LOS State Machine ✓✓✓ ✓✓
RX Polarity ✓✓✓ ✓✓
PRBS Checker ✓✓✓ ✓✓ ✓
5x Over-sampler ✓✓✓ ✓✓