Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 53
UG196 (v1.3) May 25, 2007
Package Placement Information
R
Figure 4-2: XC5VLX30T-FF665, XC5VLX50T-FF665, XC5VSX35T-FF665, and XC5VSX50T-FF665 GTP Placement
MGTAVCCPLL_116
MGTAVCC_116
MGTAVCC_116
MGTAVCC_112
MGTAVCC_112
MGTAVCC_114
MGTAVCC_114
MGTAVCC_118
MGTAVCC_118
MGTAVCCPLL_112
MGTAVCCPLL_114
MGTAVCCPLL_118
F3D4
D3
E3F1
E4E1
C3
C1
D1
B3G2
G3
F2
B2
C2
M3K4
K3
L3M1
L4L1
J3
J1
K1
H3N2
N3
M2
H2
J2
V3T4
T3
U3V1
U4U1
R3R1
T1
P3W2
W3V2
P2
R2
Power Pins
XC5VLX30T: GTP_DUAL_X0Y3
XC5VLX50T: GTP_DUAL_X0Y4
XC5
VSX35T: GTP_DUAL_X0Y3
XC5VSX50T: GTP_DUAL_X0Y3
XC5VLX30T: GTP_DUAL_X0Y2
XC5VLX50T: GTP_DUAL_X0Y3
XC5VSX35T: GTP_DUAL_X0Y2
XC5VSX50T: GTP_DUAL_X0Y2
XC5VLX30T: GTP_DUAL_X0Y1
XC5VLX50T: GTP_DUAL_X0Y2
XC5VSX35T: GTP_DUAL_X0Y1
XC5VSX50T: GTP_DUAL_X0Y1
XC5VLX30T: GTP_DUAL_X0Y0
XC5VLX50T: GTP_DUAL_X0Y1
XC5VSX35T: GTP_DUAL_X0Y0
XC5VSX50T: GTP_DUAL_X0Y0
Right Edge of the Die
AD3AB4
AB3
AC3AD1
AC4AC1
AA3AA1
AB1
AE3AE2
MGTAVTTTX_118
MGTAVTTTX_118
MGTAVTTRX_118
MGTAVTTTX_114
MGTAVTTTX_114
MGTAVTTRX_114
MGTAVTTTX_112
MGTAVTTTX_112
MGTAVTTRX_112
MGTAVTTTX_116
MGTAVTTTX_116
MGTAVTTRX_116
Y3AD2
Y2
MGTTXN0_118
MGTTXP0_118
MGTTXN1_118
MGTTXP1_118
MGTRXN0_118
MGTRXP0_118
MGTRXN1_118
MGTRXP1_118
MGTREFCLKP_118
MGTREFCLKN_118
MGTTXN0_114
MGTTXP0_114
MGTTXN1_114
MGTTXP1_114
MGTRXN0_114
MGTRXP0_114
MGTRXN1_114
MGTRXP1_114
MGTREFCLKP_114
MGTREFCLKN_114
MGTTXN0_112
MGTTXP0_112
MGTTXN1_112
MGTTXP1_112
MGTRXN
0_112
MGTRXP0_112
MGTRXN1_112
MGTRXP1_112
MGTREFCLKP_112
MGTREFCLKN_112
MGTTXN0_116
MGTTXP0_116
MGTTXN1_116
MGTTXP1_116
MGTRXN0_116
MGTRXP0_116
MGTRXN1_116
MGTRXP1_116
MGTREFCLKP_116
MGTREFCLKN_116
AA2
UG196_c4_02_012007

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English