Xilinx Virtex-5 RocketIO GTP

54 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 4: Implementation
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Figure 4-3: XC5VLX50T-FF1136, XC5VLX85T-FF1136, XC5VLX110T-FF1136, XC5VSX50T-FF1136, and XC5VSX95T-FF1136 GTP Placement (1 of 2)
D3 MGTAVCCPLL_120E4 MGTREFCLKP_120
XC5VLX50T: GTP_DUAL_X0Y5
XC5VLX85T: GTP_DUAL_X0Y5
XC5VLX110T: GTP_DUAL_X0Y6
XC5VSX50T: GTP_DUAL_X0Y5
XC5VSX95T: GTP_DUAL_X0Y6
D4 MGTREFCLKN_120
D5 MGTAVCC_120
F4 MGTAVCC_120
D1 MGTRXP1_120
C1 MGTRXN1_120
C3 MGTAVTTRX_120A3 MGTRXP0_120
A2 MGTRXN0_120
C4 MGTAVTTTX_120
E3 MGTAVTTTX_120
E2 MGTTXP1_120
D2 MGTTXN1_120
B4 MGTTXP0_120
B3 MGTTXN0_120
C6 MGTAVCCPLL_124D8 MGTREFCLKP_124
Power PinsRight Edge of the Die
XC5VLX50T: Not Available
XC5VLX85T: Not Available
XC5VLX110T: GTP_DUAL_X0Y7
XC5VSX50T: Not Available
XC5VSX95T: GTP_DUAL_X0Y7
C8 MGTREFCLKN_124
C7 MGTAVCC_124
D7 MGTAVCC_124
A6 MGTRXP1_124
A7 MGTRXN1_124
C9 MGTAVTTRX_124A9 MGTRXP0_124
A8 MGTRXN0_124
C10 MGTAVTTTX_124
C5 MGTAVTTTX_124
B5 MGTTXP1_124
B6 MGTTXN1_124
B10 MGTTXP0_124
B9 MGTTXN0_124
K3 MGTAVCCPLL_116H4 MGTREFCLKP_116
XC5VLX50T: GTP_DUAL_X0Y4
XC5VLX85T: GTP_DUAL_X0Y4
XC5VLX110T: GTP_DUAL_X0Y5
XC5VSX50T: GTP_DUAL_X0Y4
XC5VSX95T: GTP_DUAL_X0Y5
H3 MGTREFCLKN_116
J3 MGTAVCC_116
J4 MGTAVCC_116
K1 MGTRXP1_116
J1 MGTRXN1_116
G3 MGTAVTTRX_116G1 MGTRXP0_116
H1 MGTRXN0_116
F3 MGTAVTTTX_116
L3 MGTAVTTTX_116
L2 MGTTXP1_116
K2 MGTTXN1_116
F2 MGTTXP0_116
G2 MGTTXN0_116
T3 MGTAVCCPLL_112P4 MGTREFCLKP_112
XC5VLX50T: GTP_DUAL_X0Y3
XC5VLX85T: GTP_DUAL_X0Y3
XC5VLX110T: GTP_DUAL_X0Y4
XC5VSX50T: GTP_DUAL_X0Y3
XC5VSX95T: GTP_DUAL_X0Y4
P3 MGTREFCLKN_112
R3 MGTAVCC_112
R4 MGTAVCC_112
T1 MGTRXP1_112
R1 MGTRXN1_112
N3MGTAVTTRX_112N1 MGTRXP0_112
P1 MGTRXN
0_112
U3 MGTAVTTTX_112
M3 MGTAVTTTX_112
U2 MGTTXP1_112
T2 MGTTXN1_112
M2 MGTTXP0_112
N2 MGTTXN0_112
UG196_c4_03_012007