Xilinx Virtex-5 RocketIO GTP User Manual

30 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 1: Introduction to the RocketIO GTP Transceiver
R
TXDATA0
TXDATA1
In TXUSRCLK2 Transmitting data bus.
FPGA TX Interface
(page 90)
TXDATAWIDTH0
TXDATAWIDTH1
In TXUSRCLK2 Selects the width of the TXDATA port.
FPGA TX Interface
(page 90)
TXDETECTRX0
TXDETECTRX1
In TXUSRCLK2
Activates the receiver detection feature
for PCI Express.
Power Control
(page 81), PCI Express
Receive Detect Support
(page 117)
TXDIFFCTRL0[2:0]
TXDIFFCTRL1[2:0]
In Async
Controls the transmitter differential
output swing.
Configurable TX Driver
(page 113)
TXELECIDLE0
TXELECIDLE1
In TXUSRCLK2
Drives TXN and TXP to the same
voltage to perform PCI Express
electrical idle/beaconing.
Power Control
(page 81), TX
OOB/Beacon Signaling
(page 119)
TXENC8B10BUSE0
TXENC8B10BUSE1
In TXUSRCLK2 Enables the 8B/10B encoder.
Configurable 8B/10B
Encoder (page 100),
FPGA TX Interface
(page 90)
TXENPMAPHASEALIGN In Async
Allows both GTP transceivers in a
GTP_DUAL tile to align their XCLKs
with their TXUSRCLKs, allowing their
TX buffers to be bypassed, and allows
the XCLKs in multiple GTPs to be
synchronized.
TX Buffering, Phase
Alignment, and Buffer
Bypass (page 104)
TXENPRBSTST0[1:0]
TXENPRBSTST1[1:0]
In TXUSRCLK2
Transmitter test pattern generation
control.
TX PRBS Generator
(page 109)
TXINHIBIT0
TXINHIBIT1
In TXUSRCLK2 Inhibits data transmission.
TXKERR0[1:0]
TXKERR1[1:0]
Out TXUSRCLK2
Indicates if an invalid code for a K
character was specified.
Configurable 8B/10B
Encoder (page 100)
TXOUTCLK0
TXOUTCLK1
Out N/A
Provides a parallel clock generated by
the internal dividers of the GTP
transceiver.
Note: When INTDATAWIDTH = 1, the
duty cycle is 60/40 instead of 50/50.
TXOUTCLK cannot drive TXUSRCLK
when the TX phase-alignment circuit is
used.
FPGA TX Interface
(page 91), TX Buffering,
Phase Alignment, and
Buffer Bypass (page 104)
TXPMASETPHASE In Async
Aligns XCLK with TXUSRCLK for both
GTP transceivers in the GTP_DUAL
tile.
TX Buffering, Phase
Alignment, and Buffer
Bypass (page 104)
TXPOLARITY0
TXPOLARITY1
In TXUSRCLK2
Specifies if the final transmitter output
is inverted.
TX Polarity Control
(page 108)
Table 1-3: GTP_DUAL Port Summary (Continued)
Port Dir Domain Description Section (Page)

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English