Xilinx Zynq UltraScale+ ZCU216 User Manual

The following gure shows a high-level view of the I2C1 bus connecvity.
Figure 8: I2C1 Bus Topology
TCA9548A
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
SD4/SC5
SD5/SC5
SD6/SC6
SD7/SC7
IIC_EEPROM_SDA/SCL
S15341_SDA/SCL
USER_S1570__C0_SDA/SCL
USER_MGT_S1570_SDA/SCL
8A34001_SDA/SCL
CLK104_SDA/SCL
RFMC_I2C_SDA/SCL
Not Connected
SDA/SCL
BANK 500
PS I2C1
U1
BANK 89
U1
MPS430
U38
28 P4_1
29 P4_2
L/S
U18
0x74
U19
U20
I2C1_SDA/SCL
L/S
MIO17/
MIO16
PL I2C1
TCA9548A
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
SD4/SC5
SD5/SC5
SD6/SC6
SD7/SC7
FMCP_HSPC_II_SDA/SCL
USER_SI570_C1_SDA/SCL
SYSMON_SDA/SCL
PS_DDR4_SODIMM_SDA/SCL
SFP3_IIC_SDA/SCL
SFP2_IIC_SDA/SCL
SFP1_IIC_SDA/SCL
SFP0_IIC_SDA/SCL
SDA/SCL
0x75
U22
D9/C9
X23320-100119
The addresses of each target device on the I2C1 U20 and U22 PCA9548A switches are
idened in the following tables.
Table 11: I2C1 TCA9548A U20 Target Device Addresses
TCA9548A U20 (Addr 0x74) Port I2C1 Bus Device Target Device Address
0 EEPROM U16 0X54
1 Si5341 Clock U43 0x76
2 USER Si570 C0 Clock U47 0X5D
3 USER MGT Si570 Clock U48 0X5D
4 8A34001 (zSFP ClK Recovery) U409 0x58
5 CLK104 Connector J101 0x2F
6 RFMC LPAF-50 Connector J82 USER
Chapter 3: Board Component Descriptions
UG1390 (v1.1) July 10, 2020 www.xilinx.com
ZCU216 Board User Guide 34
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Xilinx Zynq UltraScale+ ZCU216 Specifications

General

Brand	Xilinx
Model	Zynq UltraScale+ ZCU216
Category	Motherboard
Language	English