Xilinx Zynq UltraScale+ ZCU216 User Manual

These oscillators can also be reprogrammed from MSP430 system controller U38 (see TI
MSP430 System Controller on the Texas Instruments website for more system controller
informaon and the ZCU216 web page for the ZCU216 System Controller GUI Tutorial (XTP_TBD).
DDR4 Memory Interface C0 (U47) and C1 (U130) SI570:
• Programmable oscillator: Silicon Labs Si570BAB001614DG (10 MHz-810 MHz, 300 MHz
default)
• I2C 0x5D
• LVDS dierenal output
• Total Stability: 61.5 ppm
GTY SI570:
• Programmable oscillator: Silicon Labs Si570BAB000544DG (10 MHz-810 MHz, 156.250 MHz
default)
• I2C 0x5D
• LVDS dierenal output
• Total stability: 61.5 ppm
The SI5341B and SI570 data sheets can be found on the Silicon Labs website.
User SMA MGT Clock
[Figure 2, callout 34]
The ZCU216 board provides a pair of SMAs (J6, J7) for dierenal AC coupled user MGT clock
input into Zynq UltraScale+ RFSoC U1 GTY Bank 130. This dierenal signal pair is series-
capacitor coupled. The P-side SMA J6 signal USER_SMA_MGT_CLOCK_P is connected to U1
MGTREFCLK1P pin M34, and the N-side SMA J7 signal USER_SMA_MGT_CLOCK_N is
connected to U1 MGTREFCLK1N pin M35. The user SMA MGT clock dierenal signal
amplitude must not exceed -0.5V (Min) to 1.30V (Max).
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU216 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
zSFP/zSFP+ Module Connectors
[Figure 2, callout 15]
The ZCU216 board hosts a quad zSFP/zSFP+ connector (J29) that accept zSFP or zSFP+
modules. The connectors are housed within a single 2x2 zSFP cage assembly. The following
gure shows the zSFP/zSFP+ module locaons within J29.
Chapter 3: Board Component Descriptions
UG1390 (v1.1) July 10, 2020 www.xilinx.com
ZCU216 Board User Guide 48
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Xilinx Zynq UltraScale+ ZCU216 Specifications

General

Brand	Xilinx
Model	Zynq UltraScale+ ZCU216
Category	Motherboard
Language	English