Xilinx Zynq UltraScale+ ZCU216 User Manual

Appendix B
Xilinx Design Constraints
Overview
The Xilinx design constraints (XDC) le template for the ZCU216 board provides for designs
targeng the ZCU216 evaluaon board. Net names in the constraints listed correlate with net
names on the latest ZCU216 evaluaon board schemac. Idenfy the appropriate pins and
replace the net names with net names in the user RTL. See the Vivado Design Suite User Guide:
Using Constraints (UG903) for more informaon.
The HSPC FMCP connector J28 is connected to Zynq
®
UltraScale+™ RFSoC U1 banks powered
by the variable voltage VADJ_FMC. The FMC bank I/O standards must be uniquely dened by
each customer because dierent FMC cards implement dierent circuitry.
IMPORTANT!
See the ZCU216 board documentaon ("Board Files" check box) for the XDC le.
Appendix B: Xilinx Design Constraints
UG1390 (v1.1) July 10, 2020 www.xilinx.com
ZCU216 Board User Guide 69
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Xilinx Zynq UltraScale+ ZCU216 Specifications

General

Brand	Xilinx
Model	Zynq UltraScale+ ZCU216
Category	Motherboard
Language	English