Xilinx Zynq UltraScale+ ZCU216 User Manual

Table 16: Ethernet PHY LED Functional Description (cont'd)
Pin
Type Description
Name Number
LED_0 63 S, I/O, PD
By default, this pin indicates that link is established.
Additional functionality is configurable by means of LEDCR1[3:0] register bits.
The LED funcons can be re-purposed with a LEDCR1 register write available through the PHYs
management data interface, MDIO/MDC. LED_2 is assigned to ACT (acvity indicator) and
LED_0 indicates link established.
LED_1 (100BASE-T link established) is a separate LED DS8 located on the top side of the board
near the RJ45 P1 connector (Figure 2, callout 16).
For more Ethernet PHY details, see the TI DS83867 data sheet on the Texas Instruments
website.
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU216 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
Programmable Logic JTAG Programming Options
[Figure 2, callouts 8 and 9]
ZCU216 JTAG chain:
• J24 USB micro AB connector connected to U29 FT4232HL USB-JTAG bridge
• J25 2x7 2 mm shrouded, keyed JTAG pod at cable connector
The ZCU216 board JTAG chain is shown in the following gure.
Chapter 3: Board Component Descriptions
UG1390 (v1.1) July 10, 2020 www.xilinx.com
ZCU216 Board User Guide 43
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Xilinx Zynq UltraScale+ ZCU216 Specifications

General

Brand	Xilinx
Model	Zynq UltraScale+ ZCU216
Category	Motherboard
Language	English