Xilinx Zynq UltraScale+ ZCU216 User Manual

For addional informaon on GTY transceivers, see the UltraScale Architecture GTY Transceivers
User Guide (UG578).
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU216 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
PS GTR Transceivers
The PS-side GTR transceiver Bank 505 supports USB (3.0) and SATA, with two channels not
used.
Bank 505 USB0 lane 2 supports the USB0 (USB3.0) interface documented in the USB 3.0
Transceiver and USB 2.0 ULPI PHY secon. The PS-Side GTR transceiver is used to provide USB
3.0 Host-Only connecvity.
Bank 505 SATA lane 3 supports SATA connector U36 shown in Figure 18: M.2 Connector.
Bank 505 reference clocks are connected to the U43 SI5341B clock generator as detailed in
SI5341B 10 Independent Output Any-Frequency Clock Generator U43.
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU216 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
PS M.2 SATA Connector
[Figure 2, callout 31 and 32]
The M.2 SATA interface is provided for SATA SSD access using the PS-Side bank 505 GTR
transceiver. The following gure shows M.2 connector U36.
The Socket 2 SATA adapter pinout with Key M is shown in the table below. SATA-A data
connecon is used for TX and SATA-B for RX. The M.2 connector U36 is a type 2242 (acve
component secon 22 mm wide with overall length 42 mm form factor) used on Socket 2.
Chapter 3: Board Component Descriptions
UG1390 (v1.1) July 10, 2020 www.xilinx.com
ZCU216 Board User Guide 56
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Xilinx Zynq UltraScale+ ZCU216 Specifications

General

Brand	Xilinx
Model	Zynq UltraScale+ ZCU216
Category	Motherboard
Language	English