ABB REL650 - Page 121

PHSL1
PHSL1L2
PHSL2L3
STFWL2
STFWL3
FWL1
FWL2
FWL1L2
FWL3
FWL2L3
FWL3L1
BLOCK
VTSZ
OR
t
15 ms
AND
AND
AND
AND
AND
AND
AND
OR
OR
OR
OR
IN present
t
15 ms
AND
t
15 ms
AND
STFWPE
AND
=1
=2
=3
STFW1PH
STFW2PH
STFW3PH
IEC12000134-2-en.vsd
IEC12000134 V2 EN-US
Figure 47: Additional start outputs 2
PHSL1
PHSL1L2
PHSL2L3
STRVL2
STRVL3
RVL1
RVL2
RVL1L2
RVL3
RVL2L3
RVL3L1
BLOCK
VTSZ
OR
t
15 ms
AND
AND
AND
AND
AND
AND
AND
OR
OR
OR
OR
IN present
t
15 ms
AND
t
15 ms
AND
STRVPE
AND
IEC12000141-2-en.vsdx
IEC12000141 V2 EN-US
Figure 48: Additional start outputs 3
1MRK 506 382-UEN A Section 6
Impedance protection
Line distance protection REL650 2.2 IEC 115
Technical manual