Avnet Qseven MSC Q7-BT - PCI Express

MSC Q7-BT MSC_Q7-BT_User_Manual.pdf 32 / 113
4.4 PCI Express
The Bay Trail-I SoC supports four PCIe lanes.
One PCIe lane is used for connecting the ethernet controller on the module.
The remaining three PCIe x1 lanes are routed to the carrier board.
On request a special BIOS version can be provided which combines PCIe lanes 0 and 1 into a x2 PCIe port.
Table 4-4 PCIe Signal Description
Signal
Pin Type
Signal Level
Available
Power
Tolerance
PU/PD
Description
PCIE_TX[0..2]+
PCIE_TX[0..2]-
O
PCIe
Full On
AC coupled
on module
PCI Express Differential Transmit Pairs
PCIE_RX[0..2]+
PCIE_RX[0..2]-
I
PCIe
Full On
PCI Express Differential Receive Pairs
PCIE_CLK_REF+
PCIE_CLK_REF-
O
PCIe
Full On
PCI Express Reference Clock