Interlaced Scan CCD Sensor
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Pixels Pixels Pixels Pixels
Horizontal
Shift Register
ADC VGC
= Field 0
Readout
= Field 1
Readout
Fig. 30: CCD Sensor Architecture - Interlaced Scan Sensors
Sensor
ADC
FPGA
Ethernet
Controller
Image
Buffer
Image
Data
Image
Data
I/O
Acquisition Start Trigger Signal or
Frame Start Trigger Signal or
Frame Counter Reset Signal or
Trigger InputCounter Reset Signal
Acquisition Trigger Wait Signal or
Frame Trigger Wait Signal or
Exposure Active Signal or
Timer 1 Signal
Micro-
Controller
Control
Data
Image Data
and
Control Data
Ethernet
Network
Image
Data
Control
VGC
Control:
AOI, Gain, Black Level
Fig. 31: Camera Block Diagram