Product Overview 1-43
Physical Description
Figure 1-15 Fast Ethernet Interface Processor
Following are the product numbers associated with the FEIP:
• CX-FEIP-1TX= (interface processor with one 100BaseTX port adapter)
• CX–FEIP-2TX= (interface processor with two 100BaseTX port adapters)
The interfaces on an FEIP can each be configured for half duplex (HDX) or full duplex (FDX), for
a maximum aggregate bandwidth of 200 Mbps. The FEIP microcode boot image resides in an
EPROM in socket location U37.
For maximum port densities, refer to the section “Port Densities” in this chapter.
Token Ring Interface Processor (TRIP)
The TRIP, shown in Figure 1-16, provides two or four Token Ring ports for interconnection with
IEEE-802.5 and IBM Token Ring media. The TRIP uses the IBM 16/4-Mbps chipset with an
imbedded performance-enhanced interface driver and a 16.7-MHz bit-slice processor for high-speed
processing. The speed on each port is set independently with a software command for either 4 or
16 Mbps. The default TRIP microcode resides on a ROM in socket U41.
H2940
DRAM
SIMMs
icrocode
ROM U37
Bus connector
MII RJ-45
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