Commodore Amiga - Page 294

QUICK REE'ERENCE •• BRIEF ADDRESS MAP FOR 8520S
The systEm hardware selects the 8520s (also called CIAs) when the
upper three address bits are 101. Furthermore, ClM is selected
when Al2 is low, Al3 high; CIAB is selected when Al2 is high, Al3 low.
You can use either byte or word addresses to access the 8520s.
For byte access (seems to be the usual case), AO must be 0 for ClM,
1 for CIAB. For word access, CIAB COIIIIIUl1icates on data bits 15-8;
ClM conmmicates on data bits 7-0. (AO is always 0 for word access,
natura11y.)
Address bits All, AlO, A9, and AS are used to specify which of the 16
internal registers you want to access. This is indicated by "r" in
the address. A11 other bits are don't cares. So, ClM is selected
by the fo11owing binary address: 10lx xxxx xxOl rrrr xxxx xxxO.
CIAB address: 10lx xxxx xxlO rrrr xxxx xxx!
With future expansion in mind, we have decided on the following
addresses: ClM = BFErOl; CIAB = BFDrOO.
CIAB Address Map
Byte Register
Address Name 7 6
Data bits
543 2 1 o
BFDOOO
BFDIOO
BFD200
BFD300
BFD400
BFD500
BFD600
BFD700
BFD800
BFD900
BFDA.OO
BFDBOO
BFDCOO
BFOOOO
BFDEOO
BFDE'OO
/fYJ:R /RTS /CD /crs /DSR SEL POUT BUSY
/MTR /SEL3 /SEL2 /SELl /SELO /SlDE DlR /STEP
ddr for port A (BFDOOO); 1 = output (set to OXCO)
ddr for port B (BFDIOO); 1 = output (set to OxFF)
CIAB timer A low byte
CIAB timer A high byte
ClAB timer B low byte
CIAB timer B high byte
Horizontal sync event counter bits 7-0
Horizontal sync event counter bits 15-8
Horizontal sync event counter bits 23-16
not used
ClAB serial data register
CIAB interrupt control register
CIAB Control register A
CIAB Control register B
Note: CIAB can generate INT6.
CIAA Address Map
Byte Register
Address Name 7 6
Data bits
4 3
o
2
1
5
BFEOOl
BFEIOl
BFE201
BFE301
BFE401
BFE50l
BFE60l
BFE701
BFEBOl
BFE901
BFEAOl
BFEBOl
BFECOl
BFEDOl
BFEEOl
BFEFOl
/FIRl /FIRO /BDY /TKO jWPRO /CHNG IUD OVL
Para11e1 port
ddr for port A (BFEOOl); l=output (set to OX03)
ddr for port B (BFElOl) ;l=output (can be in or out)
ClM timer A low byte
ClM timer A high byte
ClM timer B low byte
ClM timer B high byte
60 Hz event counter bits 7-0
60 Hz event counter bits 15-8
60 Hz event counter bits 23-16
not used
ClM serial data register (keyboard)
ClM interrupt control register
ClM control register A
ClM control register B
Note: ClM can generate INT2.
............................................................. , .....
INTERFACE SIGNALS
Clock input
The 02 clock is a TTL COIIpatib1e input used for internal device
operation and as a timing reference for COIIIIIUl1icating with the
systEm data bus.
CS - chip-select input
The CS input controls the activity of the 8520. A low level on CS.
while 02 is high causes the device to respond to signals on the R/W
and address (RS) lines. A high on CS prevents these lines from
contro11ing the 8520. The CS line is norma11y activated (lOW) at
02 by the appropriate address combination.
R/W - read/write input
The R/W signal is norma11y supplied by the microprocessor and
controls the direction of data transfers of the 8520. A high on
R/W indicates a read (data transfer out of the 8520), while a
low indicates a write (data transfer into the 8520) •