Commodore Amiga - Page 298

OUTPUT K>DE
In the output mode, Timer A is used as the baud rate generator.
Data is shifted out on the SP pin at 1/2 the underflow rate of
T~.mer A. The maxilrrum baud rate possible is 02 divided by 4, but
the maxinrum usable baud rate will be detennined by line loading and
the speed at which the receiver responds to input data.
To begin transmission, you must first set up Timer A in continuous
mode, and start the timer. Transmission will start following a
write to the serial data register. The clock signal derived from
Timer A appears as an output on the CNT pin. The data in the serial
data register will be loaded into the shift register, then shifted
out to the SP pin when a CNT pulse occurs. Data shifted out
becomes valid on the next falling edge of CNT and remains valid
until the next falling edge.
After eight CNT pulses, an interrupt is generated to indicate that
more data can be sent. If the serial data register was reloaded
with new information prior to this interrupt, the new data will
automatically be loaded into the shift register and transmission
will continue.
If no further data is to be transmitted after the eighth CNT pulse,
CNT will return high and SP will remain at the level of the last
data bit transmitted.
SDR data is shifted out MSB first. Serial input data should appear
in this same format.
BIDIRECTIONAL FEA'l'URE
'!be bidirectional capability of the serial port and CNT clock allows
many 8520s to be connected to a conmon serial colllllUnications bus on
which one 8520 acts as a master, sourcing data and shift clock,
while all other 8520 chips act as slaves. Both CNT and SP outputs
are open drain to allow such a conmon bus. Protocol for
master/slave selection can be transmitted over the serial bus or
via dedicated handshake lines.
REG NAME
D7 D6 D5 D4 D3 D2 D1 DO
c
SDR
57 S6 S5 54 S3 S2 S1 SO
INTERRUPT CONTROL REGISTER (ICR)
'lbere are five sources of interrupts on the 8520:
-Underflow from Timer A (timer counts down past 0)
-Underflow from Timer B
-TOD alarm
-Serial port full/enpty
-Flag
A single register provides masking and interrupt information. '!be
interrupt control register consists of a write-only MASK register
and a read-only DATA register. Any interrupt will set the
corresponding bit in the DATA register. Any interrupt that is
enabled by a 1-bit in that position in the MASK will set theIR bit
(MSB) of the DATA register and bring the IRQ pin low. In a
multichip system, the IR bit can be polled to detect which chip has
generated an interrupt request.
When you read the DATA register, its contents are cleared (set to 0),
and the IRQ line returns to a high state. Since it is cleared on a
read, you must assure that your interrupt polling or interrupt service
code can preserve and respond to all bits which may have been set in
the DATA register at the time it was read. With proper preservation
and response, it is easily possible to intermix polled and direct
interrupt service methods.
You can set or clear one or more bits of the MASK register without
affecting the current state of any of the other bits in the register.
This is done by setting the appropriate state of the MSBit, which is
called the set/clear bit. In bits 6-0, you yourself form a mask
that specifies which of the bits you wish to affect. Then, using
bit 7, you specify HOW the bits in corresponding positions in the
mask are to be affected.
o If bit 7 is a 1, then any bit 6-0 in your own mask word
which is set to a 1 sets the corresponding bit in the
MASK register. Any bit that you have set to a 0 causes
the MASK register bit to remain in its current state.
o If bit 7 is a 0, then any bit 6-0 in your own mask word
which is set to a 1 clears the corresponding bit in the MASK
register. Again, any 0 bit in your own mask word causes no
change in the contents of the corresponding MASK register bit.
I f an interrupt is to occur based on a particular condition,
then that corresponding MASK bit must be a 1.
Exanple: Suppose you want to set the Timer A interrupt bit
(enable the Timer A interrupt), but want to be
sure that all other interrupts are cleared. Here
is the sequence you can use:
movi.b 01111110B,AO
mov.b AO,ICR ;MSB is 0, means clear
;any bit whose value is
; 1 in the rest of the byte
movi.b 10000001B,AO
mov.b AO,ICR ;MSB is 1, means set
;any bit whose value is
; 1 in the rest of the byte
; (do not change any values
; wherein the written value
; bit is a zero)