Commodore Amiga - Page 297

One-shot/continuous
A control bit selects either timer mode. In one-shot mode,
the timer will count down from the latched value to zero,
generate an interrupt, reload the latched value, then stop.
In continuous mode, the timer will count down from the
latched value to zero, generate an interrupt, reload the
latched value, and repeat the procedure continuously.
In one-shot mode, a write to timer-high (register 5 for
timer A, register 7 for Timer B) will transfer the timer
latch to the counter and initiate counting regardless of
the start bit.
Force load
INPUT K>DES
A strobe bit allows the timer latch to be loaded into the
timer counter at any time, whether the timer is running or
not.
Control bits allow selection of the clock used to decrement the
timer. Timer A can count 02 clock pulses or external pulses
applied to the CNT pin. Timer B can count 02 pulses, external
CNT pulses, timer A underflow pulses, or timer A underflow pulses
while the CNT pin is held high.
The timer latch is loaded into the timer on any timer underflow, on
a force load, or following a write to the high byte of the pre-
scalar while the timer is stopped. If the timer is running, a write
to the high byte will load the timer latch but not the counter.
BIT NAMES on READ-register
REG NAME 07 D6 05 D4 03 02 01 DO
4
5
6
7
TALO
TAHI
TBLO
TBHI
TAL 7 TAL6 TALS TAL4 TAL3 TAL2
TALI TALO
TAH7 TAR6 TAH5 TAR4 TAR3 TAR2 TAHl TARO
TBL 7 TBL6 TBLS TBL4 TBL3 TBL2 TBLI TBLO
TBH7 TBH6 TBH5 TBH4 TBH3 TBH2 TBHl TBHO
BIT NAMES on WRITE-register
REG NAME 07 D6 05 D4 03 02 01 DO
4
5
6
7
TALC
TAHI
TBLO
TBHI
PAL 7 PAL6 PALS PAL4 PAL3 PAL2 PALl PALO
PAIr7 PAR6 PARS PAR4 PAR3 PAH2 PAR1 PARO
PBL 7 PBL6 PBLS PBL4 PBL3 PBL2 PBL1 PBLO
PBH7 PBH6 PBHS PBH4 PBH3 PBH2 PBHl PBHO
TIME OF DAY CLOCK
TOO consists of a 24-bit binary counter. Positive edge transitions
on this pin cause the binary counter to increment. The TOO pin has a
passive pull-up on it.
A programmable alarm is provided for generating an interrupt at a
desired time. The alarm registers are located at the same addresses
as the corresponding TOO registers. Access to the alarm is governed
by a control register bit. The alarm is write-only; any read of a
TOO address will read time regardless of the state of the ALARM
access bit.
A specific sequence of events nrust be followed for proper setting and
reading of TOO. TOO is automatically stopped whenever a write to the
register occurs. The clock will not start again until after a
write to the LSB event register. This assures that TOO will always
start at the desired time.
Since a carry from one stage to the next can occur at any time
with respect to a read operation, a latching function is included
to keep all TOO information constant during a read sequence.
All TOO registers latch on a read of MEB event and remain latched
until after a read of LSB event. The TOO clock continues to count
when the output registers are latched. If only one register is to
be read, there is no carry problem and the register can be read
"on the fly" provided that any read of MEB event is followed by a
read of LSB Event to disable the latching.
BIT NAMES for WRITE TIME/ALARM or READ TIME
REG NAME
8
LSB Event E7
E6
ES E4
E3
E2
9
Event 8-15 E1S
E14 El3 E12
Ell E10
A
MEB Event E23
E22 E21 E20
E19 E18
WRITE
CRB7 = 0
CRB7 = 1 ALARM
SERIAL PORT (SDR)
E1 EO
E9 E8
E17
E1G
The serial port is a buffered, 8-bit synchronous shift register.
A control bit selects input or output mode.
INPUT K>OE
In input mode, data on the SP pin is shifted into the shift
register on the rising edge of the signal applied to the CNT pin.
After eight CNT pulses, the data in the shift register is dUllped
into the serial data register and an interrupt is generated.