Commodore Amiga - Page 296

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~
Address for:
-----------------
8520-A
8520-B
I NAME I
EXPLANATION
-------------------------------------------------
(write)/(read mode)
BFEOOl
BFOOOO
PRA
Peripheral data register A
BFEIOl
BFOIOO PRB
Peripheral data register B
BFE201
BF0200 OORB
Data direction register "A"
BFE301
BF0300 DORA
Data direction register "B"
BFE401
BFD400 TALC
TIMER A low register
BFESOl
BFOSOO TAHI
TIMER A high register
BFE601
BFD600 TBLO
TIMER B low register
BFE?Ol
BFO?OO TBHI
TIMER B high register
BFE801
BFD800 Event LSB
BFE901 BFD900
Event 8 - 15
BFEAOl
BFDAOO Event MSB
BFEBOl
BFOBOO No connect
BFECOl
BFDCOO SOR
Serial data register
BFEOOl BFDOOO
ICR
Interrupt control register
BFEEOl
BFOEOO CRA
Control register A
BFEFOl
BFDFOO CRB
Control register B
REGISTER FUNCTIONAL DESCRIPTION:
I/O PORTS (PRA, PRB, DORA, DDRB)
Ports A and B each consist of an a-bit peripheral data register (PR)
and an a-bit data direction register (OOR). If a bit in the OOR is
set to a 1, the corresponding bit position in the PR becomes an
output. I f a OOR bit is set to a 0, the corresponding PR bit is
defined as an input.
When you READ a PR register, you read the actual current state of
the I/O pins (PAO-PA?, PBO-PB?, regardless of whether you have set
them to be inputs or outputs.
Ports A and B have passive pull-up devices as well as active
pull-ups, providing both CMOS and TTL corrpatibility. Both ports
have two TTL load drive capability.
In addition to their normal I/O operations, ports PB6 and PB? also
provide timer output functions.
HANDSHAKING
Handshaking occurs on data transfers using the PC output pin
and the FLAG input pin. PC will go low on the third c:yc:le
after a port B access. This signal can be used to indicate
"data ready" at port B or "data accepted" from port B.
Handshaking
on 16-bit data transfers (using both ports A and B)
is possible by always reading or writing port A first. FLAG
is a negative edge-sensitive input that can be used for
receiving the PC output from another 8520 or as a general-
purpose interrupt input. Any negative transition on FLAG
will set the FLAG interrupt bit.
REG NAME D7 D6 05 D4 D3 D2 Dl DO
o
1
2
3
PRA
PRB
DORA
DORB
PA? PA6 PAS PM PA3 PA2 PAl PAD
PB? PB6 PBS PB4 PB3 PB2 PBl PBO
DPA? DPA6 OPAS OPM OPA3 OPA2 DPAl OPAO
DPB? OPB6 OPBS DPB4 DPB3 OPB2 OPBl OPBO
INTERVAL TIMERS (TIMER A, TIMER B)
Each interval timer consists of a l6-bit read-only timer
counter and a l6-bit write-only timer latch. Data written
to the timer is latched into the timer latch, while data
read from the timer is the present contents of the timer
counter.
The latch is also called a prescalar in that it represents
the countdown value which must be counted before the timer
reaches an underflow (no more counts) condition. This latch
(prescalar) value is a divider of the input clocking frequency.
The timers can be used independently or llnked for extended
operations. Various timer operating modes allow generation
of long time delays, variable width pulses, pulse trains, and
variable frequency waveforms. Utilizing the CNT input, the
timers can count external pulses or measure frequency, pulse
Width, and delay times of external signals.
Each timer has an associated control register, providing
independent control over each of the following functions:
START/STOP
A control bit allows the timer to be started or stopped
by the microprocessor at any time.
PB on/off
A control bit allows the timer output to appear on a port B
output line (pB6 for timer A and PB? for timer B). This
function overrides the DORB control bit and forces the
appropriate PB line to become an output.
Toggle/pulse
A control bit selects the output applied to port B while
the PB on/off bit is ON. On every timer underflow, the
output can either toggle or generate a single positive
pulse of one cycle duration. The toggle output is set
high whenever the timer is started, and set low by RES.