setting the poiri ters,
43
Blitter
address scanning,
171
addressing, 170
animation, 172
area filling
exclusive, 182-3
inclusive, 180-2
blitter-finished disable bit (BFD),
23
blitter-nasty bit,
191
block transfers, 177
common equations, 174
complete example, 193
copying, 167-8
DMA priority, 186
DMA time slots, 186
equation-to-minterm conversion,
175
interrupts,
211
LF control byte, 171-7
line drawing
octants, 184
registers, 184
line drawing mode, 183-5
logic equations, 172-5
logic operations, 171-7
masking, 178-9
minterms, 173-6
modulo, 168-70
modulo registers,
169
pointer registers, 168
sequence of bus cycles, 192
shifting,
177
Venn diagrams, 175-7
with the Copper,
23
zero detection,
179
Blitter registers
in
line-drawing mode, 183-4
BLTCONO
in
line drawing, 183
in logic operations,
171
in shift control, 178
in
zero detection,
179
BLTCONI
in
area
fill,
181, 182
Index-2
in blitter addressing, 170
in line drawing, 183, 185
in shift control, 178
BL
TSIZE,
171
BLTxMOD,
169
BLTxPTH,168
BLTxPTL,
168
BPL1MOD,51
BPL2MOD,51
BPLCONO
enabling color, 52
in dual-playfield mode, 64
in hold-and-modify mode, 80
in interlacing, 40
in resolution mode,
38
selecting bit-planes,
37
setting bits,
37
with light pen, 225
BPLCON1
setting scrolling delay,
78
BPLCON2
in dual-playfield priority,
64
, 200
BPLxPTH, 43, 50,
67
BPLxPTL, 43, 50,
67
CLXCON,203
CLXDAT,203
Collision
control register, 203-4
detection register, 202-3
sprites-play fields, 202-4
Color
attached sprites,
118
background color,
35
color indirection,
31
color table,
35
enabling,
52
in dual-playfield mode,
62
in hold-and-modify mode,
79
playfields, 31-3, 34-7, 44-5, 62-63, 86-90
sample register contents, 86
sprites, 96-8
Color registers
con ten
ts
,
36
loading,
36