CURTISS-WRIGHT LIST OF TABLES
826448 VERSION 5 MARCH 2015 PROPRIETARY XI
LIST OF TABLES
Table 1.1: XMC/Expansion Plane Interface Build-Time Options for PCIe.....................................................1-8
Table 1.2: CPS-1432 SRIO Switch Port Numbering ............................................................................... 1-10
Table 1.3: Interrupt Input Connections............................................................................................... 1-26
Table 1.4: VPX Compliance Summary................................................................................................. 1-31
Table 1.5: XMC Compatibility Identification Block................................................................................. 1-31
Table 1.6: Power Requirements ......................................................................................................... 1-32
Table 1.7: CHAMP-AV8 Dimensions .................................................................................................... 1-33
Table 1.8: CHAMP-AV8 Weight .......................................................................................................... 1-33
Table 1.9: VPX6-462-A Air-Cooled Ruggedization Levels ....................................................................... 1-34
Table 1.10: VPX6-462-C Conduction-Cooled Ruggedization Levels ........................................................... 1-34
Table 1.11: Summary of CHAMP-AV8 Connectors, Functions Supported .................................................... 1-39
Table 2.1: Voltage and Current Requirements .......................................................................................2-3
Table 2.2: Maximum Supply Current for XMC Site ..................................................................................2-5
Table 2.3: Jumper Block Definition.......................................................................................................2-7
Table 3.1: CBL-462-FPL-000 USB (J1) Signal Mapping ............................................................................3-8
Table 3.2: CBL-462-FPL-000 EIA-232 Node A Serial Port 0 (J2) Signal Mapping .........................................3-8
Table 3.3: CBL-462-FPL-000 EIA-232 Node B Serial Port 0 (J3) Signal Mapping .........................................3-9
Table 3.4: CBL-462-FPL-000 Ethernet Port A (J4) Signal Mapping ............................................................3-9
Table 3.5: CBL-462-FPL-000 Ethernet Port B (J5) Signal Mapping .......................................................... 3-10
Table 3.6: CBL-462-FPL-000 Reset Pushbutton (SW1) Signal Mapping .................................................... 3-10
Table 3.7: Summary of LED Behavior ................................................................................................. 3-15
Table A.1: Wafer Usage - CHAMP-AV8 P0 Utility Connector......................................................................A-6
Table A.2: Wafer Usage - CHAMP-AV8 P1-P6 Connectors.........................................................................A-6
Table A.3: P0 Utility Connector Pin Assignments ..................................................................................A-15
Table A.4: P0 Utility Connector Signal Definitions ................................................................................. A-15
Table A.5: VPX Backplane J0 Pin Assignments .....................................................................................A-16
Table A.6: P1 SRIO Fabric Connector Pin Assignments ..........................................................................A-17
Table A.7: P1 SRIO Fabric Connector Signal Definitions......................................................................... A-18
Table A.8: VPX Backplane J1 Pin Assignments .....................................................................................A-19
Table A.9: P2 PCIe Expansion Plane Connector Pin Assignments.............................................................A-21
Table A.10: P2 PCIe Expansion Plane Connector Signal Definitions ...........................................................A-21
Table A.11: VPX Backplane J2 Pin Assignments .....................................................................................A-22
Table A.12: P3 XMC Site’s PMC User I/O Connector Pin Assignments ........................................................A-24
Table A.13: P3 XMC Site’s PMC User I/O Connector Signal Definitions.......................................................A-24
Table A.14: VPX Backplane J3 Pin Assignments .....................................................................................A-25
Table A.15: P4 Basecard I/O Connector Pin Assignments ........................................................................A-27
Table A.16: P4 Basecard I/O Connector Signal Definitions.......................................................................A-27
Table A.17: VPX Backplane J4 Pin Assignments .....................................................................................A-29
Table A.18: P5 XMC User I/O Connector Pin Assignments........................................................................ A-3
1
Table A.19: P5 XMC User I/O Connector Signal Definitions ...................................................................... A-31
Table A.20: VPX Backplane J5 Pin Assignments .....................................................................................A-32
Table A.21: P6 XMC/DIO/SATA/USB Connector Pin Assignments .............................................................. A-34
Table A.22: P6 XMC/DIO/SATA/USB Connector Signal Definitions.............................................................A-34
Table A.23: VPX Backplane J6 Pin Assignments .....................................................................................A-35
Table A.24: J1 Front Panel Connector Description .................................................................................. A-36
Table A.25: J14 Connector Description (Pn4/Jn4 User Defined I/O) ..........................................................A-40
Table A.26: J15 Primary XMC Connector Pin Assignments ....................................................................... A-43
Table A.27: J15 Primary XMC Connector Signal Definitions......................................................................A-43
Table A.28: J16 Secondary XMC Connector Pin Assignments ................................................................... A-45
Table A.29: J16 Secondary XMC Connector Signal Definitions .................................................................. A-45
Table A.30: XMC J16 User I/O Connector Description (Row A) .................................................................A-46
Table A.31: XMC J16 User I/O Connector Description (Row B) .................................................................A-47
Table A.32: XMC J16 User I/O Connector Description (Row C) .................................................................A-48
Table A.33: XMC J16 User I/O Connector Description (Row D) .................................................................A-49
Table A.34: XMC J16 User I/O Connector Description (Row E) .................................................................A-50
Table A.35: XMC J16 User I/O Connector Description (Row F) .................................................................A-51
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