CHAMP-AV8 (VPX6-462) HARDWARE USER’S MANUAL CURTISS-WRIGHT
A-34 PROPRIETARY 826448 VERSION 5 MARCH 2015
See Table A.21 below for connector pin assignments and Table A.22 for signal definitions.
Table A.21: P6 XMC/DIO/SATA/USB Connector Pin Assignments
Wafer
No.
Row G
Signal
Row F
Signal
Row E
Signal
Row D
Signal
Row C
Signal
Row B
Signal
Row A
Signal
1 DIO0 GND XMC_A5 XMC_B5 GND XMC_D5 XMC_E5
2 GND XMC_A7 XMC_B7 GND XMC_D7 XMC_E7 GND
3 DIO1 GND XMC_A9 XMC_B9 GND XMC_D9 XMC_E9
4 GND XMC_A15 XMC_B15 GND XMC_D15 XMC_E15 GND
5 DIO2 GND XMC_A17 XMC_B17 GND XMC_D17 XMC_E17
6 GND XMC_A19 XMC_B19 GND XMC_D19 XMC_E19 GND
7 DIO3 GND NC NC GND NC NC
8 GND SATA_A_TXN1 SATA_A_TXP1 GND SATA_A_RXN1 SATA_A_RXP1 GND
9 DIO4 GND SATA_B_TXN1 SATA_B_TXP1 GND SATA_B_RXN1 SATA_B_RXP1
10 GND NC NC GND NC NC GND
11 DIO5 GND NC NC GND NC NC
12 GND USB_A0_N USB_A0_P GND USB_B0_N USB_B0_P GND
13 DIO6 GND USB_A0_
POWER
NC GND USB_B0_
POWER
NC
14 GND NC NC GND NC NC GND
15 DIO7 GND DIO8 DIO9 GND DIO10 DIO11
16 GND DIO12 DIO13 GND DIO14 DIO15 GND
Table A.22: P6 XMC/DIO/SATA/USB Connector Signal Definitions
CHAMP-AV8 Signal Description
XMC_DP[9:4]_P/N
XMC_DP[19:14]_P/N
XMC Differential User I/O Mapping from XMC J16 connector to V46 P5 connector (12 pairs).
Mapped in accordance with V46.9, P5w3P6-X38s+X8d+X12d pattern.
DIO[7:0] DIO Signals - Single ended.
DIO[15:8] DIO Signals - Single ended (could be used as differential in future).
SATA_[A:B]_TX_P1/N1
SATA_[A:B]_RX_P1/N1
SATA links
USB_[A:B]0_P/N
USB_[A:B]0_PWR
USB ports
GND Ground signals as defined in VITA 46.0.
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